path: root/rr-cache/2e0fbc4890901254069ecb4576f1f83f3c3209e4/preimage

// SPDX-License-Identifier: GPL-2.0
/*
 * SDM845 SoC device tree source
 *
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
<<<<<<<
=======
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>>>>>>>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0 0x80000000 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		memory@85fc0000 {
			reg = <0 0x85fc0000 0 0x20000>;
			no-map;
		};

		memory@85fe0000 {
<<<<<<<
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85fe0000 0x0 0x20000>;
			no-map;
=======
			reg = <0x0 0x85fe0000 0x0 0x20000>;
			compatible = "qcom,cmd-db";
>>>>>>>
		};

		smem_mem: memory@86000000 {
			reg = <0x0 0x86000000 0x0 0x200000>;
			no-map;
		};

		memory@86200000 {
			reg = <0 0x86200000 0 0x2d00000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
				      compatible = "cache";
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_100>;
			L2_100: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_200>;
			L2_200: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_300>;
			L2_300: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x400>;
			enable-method = "psci";
			next-level-cache = <&L2_400>;
			L2_400: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x500>;
			enable-method = "psci";
			next-level-cache = <&L2_500>;
			L2_500: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x600>;
			enable-method = "psci";
			next-level-cache = <&L2_600>;
			L2_600: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo385";
			reg = <0x0 0x700>;
			enable-method = "psci";
			next-level-cache = <&L2_700>;
			L2_700: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
<<<<<<<
			clock-frequency = <19200000>;
=======
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
>>>>>>>
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32764>;
		};
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

<<<<<<<
=======
		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			#interrupt-cells = <3>;
			interrupt-controller;
			#redistributor-regions = <1>;
			redistributor-stride = <0x0 0x20000>;
			reg = <0x17a00000 0x10000>,     /* GICD */
			      <0x17a60000 0x100000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic-its@17a40000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x17a40000 0x20000>;
				status = "disabled";
			};
		};

>>>>>>>
		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sdm845";
			reg = <0x100000 0x1f0000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

<<<<<<<
=======
		tcsr_mutex_regs: syscon@1f40000 {
			compatible = "syscon";
			reg = <0x1f40000 0x40000>;
		};

>>>>>>>
		tlmm: pinctrl@3400000 {
			compatible = "qcom,sdm845-pinctrl";
			reg = <0x03400000 0xc00000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
<<<<<<<
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0xc440000 0x1100>,
			      <0xc600000 0x2000000>,
			      <0xe600000 0x100000>,
			      <0xe700000 0xa0000>,
			      <0xc40a000 0x26000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			cell-index = <0>;
		};

		apss_shared: mailbox@17990000 {
			compatible = "qcom,sdm845-apss-shared";
			reg = <0x17990000 0x1000>;
			#mbox-cells = <1>;
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x17a00000 0x10000>,     /* GICD */
			      <0x17a60000 0x100000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic-its@17a40000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x17a40000 0x20000>;
				status = "disabled";
			};
=======

			qup_i2c10_default: qup-i2c10-default {
				pinmux {
					function = "qup10";
					pins = "gpio55", "gpio56";
				};
			};

			qup_i2c10_sleep: qup-i2c10-sleep {
				pinmux {
					function = "gpio";
					pins = "gpio55", "gpio56";
				};
			};

			qup_uart2_default: qup-uart2-default {
				pinmux {
					function = "qup9";
					pins = "gpio4", "gpio5";
				};
			};

			qup_uart2_sleep: qup-uart2-sleep {
				pinmux {
					function = "gpio";
					pins = "gpio4", "gpio5";
				};
			};

			ufs_dev_reset_assert: ufs_dev_reset_assert {
				pins = "ufs_reset";
				bias-pull-down;		/* default: pull down */
				/*
				 * UFS_RESET driver strengths are having
				 * different values/steps compared to typical
				 * GPIO drive strengths.
				 *
				 * Following table clarifies:
				 *
				 * HDRV value | UFS_RESET | Typical GPIO
				 *   (dec)    |   (mA)    |    (mA)
				 *     0      |   0.8     |    2
				 *     1      |   1.55    |    4
				 *     2      |   2.35    |    6
				 *     3      |   3.1     |    8
				 *     4      |   3.9     |    10
				 *     5      |   4.65    |    12
				 *     6      |   5.4     |    14
				 *     7      |   6.15    |    16
				 *
				 * POR value for UFS_RESET HDRV is 3 which means
				 * 3.1mA and we want to use that. Hence just
				 * specify 8mA to "drive-strength" binding and
				 * that should result into writing 3 to HDRV
				 * field.
				 */
				drive-strength = <8>;	/* default: 3.1 mA */
				output-low; /* active low reset */
			};

			ufs_dev_reset_deassert: ufs_dev_reset_deassert {
				pins = "ufs_reset";
				bias-pull-down;		/* default: pull down */
				/*
				 * default: 3.1 mA
				 * check comments under ufs_dev_reset_assert
				 */
				drive-strength = <8>;
				output-high; /* active low reset */
			};

>>>>>>>
		};

		timer@17c90000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x17c90000 0x1000>;

			frame@17ca0000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17ca0000 0x1000>,
				      <0x17cb0000 0x1000>;
			};

			frame@17cc0000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cc0000 0x1000>;
				status = "disabled";
			};

			frame@17cd0000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cd0000 0x1000>;
				status = "disabled";
			};

			frame@17ce0000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17ce0000 0x1000>;
				status = "disabled";
			};

			frame@17cf0000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17cf0000 0x1000>;
				status = "disabled";
			};

			frame@17d00000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17d00000 0x1000>;
				status = "disabled";
			};

			frame@17d10000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17d10000 0x1000>;
				status = "disabled";
			};
		};
<<<<<<<
=======

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0xc440000 0x1100>,
			      <0xc600000 0x2000000>,
			      <0xe600000 0x100000>,
			      <0xe700000 0xa0000>,
			      <0xc40a000 0x26000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
			cell-index = <0>;
		};

		geniqup@ac0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0xac0000 0x6000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			uart2: serial@a84000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0xa84000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default", "sleep";
				pinctrl-0 = <&qup_uart2_default>;
				pinctrl-1 = <&qup_uart2_sleep>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			i2c10: i2c@a88000 {
				compatible = "qcom,geni-i2c";
				reg = <0xa88000 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default", "sleep";
				pinctrl-0 = <&qup_i2c10_default>;
				pinctrl-1 = <&qup_i2c10_sleep>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				#address-cells = <1>;
				#size-cells = <0>;
				status = "disabled";
			};
		};

		apss_shared: mailbox@17990000 {
			compatible = "qcom,sdm845-apss-shared";
			reg = <0x17990000 0x1000>;
			#mbox-cells = <1>;
		};

		apps_rsc: rsc@179e000 {
			label = "apps_rsc";
			compatible = "qcom,rpmh-rsc";
			reg = <0x179e0000 0xd00>, <0x179e0d00 0x3000>;
			reg-names = "drv", "tcs";
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <SLEEP_TCS   3>,
					  <WAKE_TCS    3>,
					  <ACTIVE_TCS  2>,
					  <CONTROL_TCS 1>;

			rpmhcc: clock-controller {
				compatible = "qcom,rpmh-clk-sdm845";
				#clock-cells = <1>;
			};

			pm8998-rpmh-regulators {
				compatible = "qcom,pm8998-rpmh-regulators";
				qcom,pmic-id = "a";

				pm8998_s1: smps1 {};
				pm8998_s2: smps2 {};
				pm8998_s3: smps3 {};
				pm8998_s4: smps4 {};
				pm8998_s5: smps5 {};
				pm8998_s6: smps6 {};
				pm8998_s7: smps7 {};
				pm8998_s9: smps9 {};
				pm8998_l1: ldo1 {};
				pm8998_l2: ldo2 {};
				pm8998_l3: ldo3 {};
				pm8998_l4: ldo4 {};
				pm8998_l5: ldo5 {};
				pm8998_l6: ldo6 {};
				pm8998_l7: ldo7 {};
				pm8998_l8: ldo8 {};
				pm8998_l9: ldo9 {};
				pm8998_l10: ldo10 {};
				pm8998_l11: ldo11 {};
				pm8998_l12: ldo12 {};
				pm8998_l13: ldo13 {};
				pm8998_l14: ldo14 {};
				pm8998_l15: ldo15 {};
				pm8998_l16: ldo16 {};
				pm8998_l17: ldo17 {};
				pm8998_l18: ldo18 {};
				pm8998_l19: ldo19 {};
				pm8998_l20: ldo20 {};
				pm8998_l21: ldo21 {};
				pm8998_l22: ldo22 {};
				pm8998_l23: ldo23 {};
				pm8998_l24: ldo24 {};
				pm8998_l25: ldo25 {};
				pm8998_l26: ldo26 {};
				pm8998_l27: ldo27 {};
				pm8998_l28: ldo28 {};
				pm8998_lvs1: lvs1 {};
				pm8998_lvs2: lvs2 {};

			};

			pmi8998-rpmh-regulators {
				compatible = "qcom,pmi8998-rpmh-regulators";
				qcom,pmic-id = "b";

				pmi8998_bob: bob {};
			};
		};

		phy@1d87000 {
			compatible = "qcom,sdm845-qmp-ufs-phy";
			reg = <0x1d87000 0x18c>;
			#clock-cells = <1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			clock-names = "ref_clk_src",
				"ref_clk",
				"ref_aux_clk";
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				<&gcc GCC_UFS_MEM_CLKREF_CLK>,
				<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

			status = "disabled";

			ufsphy_0: lane@0x1d87400 {
				reg = <0x1d87400 0x108>,
					<0x1d87600 0x1e0>,
					<0x1d87c00 0x1dc>;
				#phy-cells = <0>;
			};

			ufsphy_1: lane@0x1d87800 {
				reg = <0x1d87800 0x108>,
					<0x1d87a00 0x1e0>,
					<0x1d87c00 0x1dc>;
				#phy-cells = <0>;
			};
		};

		ufshc@1d84000 {
			compatible = "qcom,ufshc";
			reg = <0x1d84000 0x2500>;
			interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufsphy_0>, <&ufsphy_1>;
			phy-names = "ufsphy_0", "ufsphy_1";

			lanes-per-direction = <2>;
			dev-ref-clk-freq = <0>; /* 19.2 MHz */

			power-domains = <&gcc UFS_PHY_GDSC>;

			clock-names =
				"core_clk",
				"bus_aggr_clk",
				"iface_clk",
				"core_clk_unipro",
				"ref_clk",
				"tx_lane0_sync_clk",
				"rx_lane0_sync_clk",
				"rx_lane1_sync_clk";
			clocks =
				<&gcc GCC_UFS_PHY_AXI_CLK>,
				<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				<&gcc GCC_UFS_PHY_AHB_CLK>,
				<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				<&rpmhcc RPMH_CXO_CLK>,
				<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
			freq-table-hz =
				<50000000 200000000>,
				<0 0>,
				<0 0>,
				<37500000 150000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>;

			non-removable;
			pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
			pinctrl-0 = <&ufs_dev_reset_assert>;
			pinctrl-1 = <&ufs_dev_reset_deassert>;

			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "core_reset";

			status = "disabled";
		};

		tcsr_mutex_regs: syscon@1f40000 {
			compatible = "syscon";
			reg = <0x1f40000 0x40000>;
		};
>>>>>>>
	};
};