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Diffstat (limited to 'rr-cache/ece77c075cbd2f88b3ef8bcec6fb0533986e8390/preimage')
-rw-r--r-- | rr-cache/ece77c075cbd2f88b3ef8bcec6fb0533986e8390/preimage | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/rr-cache/ece77c075cbd2f88b3ef8bcec6fb0533986e8390/preimage b/rr-cache/ece77c075cbd2f88b3ef8bcec6fb0533986e8390/preimage new file mode 100644 index 0000000..2a4fbcb --- /dev/null +++ b/rr-cache/ece77c075cbd2f88b3ef8bcec6fb0533986e8390/preimage @@ -0,0 +1,40 @@ +QCOM Secure Channel Manager (SCM) + +Qualcomm processors include an interface to communicate to the secure firmware. +This interface allows for clients to request different types of actions. These +can include CPU power up/down, HDCP requests, loading of firmware, and other +assorted actions. + +Required properties: +- compatible: must contain one of the following: + * "qcom,scm-apq8064" for APQ8064 platforms + * "qcom,scm-msm8660" for MSM8660 platforms + * "qcom,scm-msm8690" for MSM8690 platforms + * "qcom,scm-msm8996" for MSM8996 platforms +<<<<<<< + * "qcom,scm-ipq4019" for IPQ4019 platforms + * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) +- clocks: One to three clocks may be required based on compatible. + * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019" +======= + * "qcom,scm-msm8998" for MSM8998 platforms + * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc) +- clocks: One to three clocks may be required based on compatible. + * No clock required for "qcom,scm-msm8996" or "qcom,scm-msm8998" +>>>>>>> + * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960" + * Core, iface, and bus clocks required for "qcom,scm" +- clock-names: Must contain "core" for the core clock, "iface" for the interface + clock and "bus" for the bus clock per the requirements of the compatible. +- qcom,dload-mode: phandle to the TCSR hardware block and offset of the + download mode control register (optional) + +Example for MSM8916: + + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + }; |