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path: root/lib/cpus/aarch64/cpu_helpers.S
AgeCommit message (Expand)Author
2023-08-10fix(cpus): assert invalid cpu_ops obtainedThaddeus Serna
2023-05-30refactor(cpus): convert print_errata_status to CBoyan Karatotev
2023-05-30refactor(cpus): rename errata_report.h to errata.hBoyan Karatotev
2023-05-30refactor(cpus): move cpu_ops field defines to a headerBoyan Karatotev
2023-03-20Merge changes from topic "bk/errata_refactor" into integrationManish Pandey
2023-03-16chore(cpus): remove redundant assertsBoyan Karatotev
2023-03-15refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3Arvind Ram Prakash
2022-03-18fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57Bipin Ravi
2021-06-03fix: random typos in tf-a code baseOlivier Deprez
2020-09-25arm_fpga: Add support for unknown MPIDsJavier Almansa Sobrino
2020-08-24lib: cpus: sanity check pointers before useVarun Wadekar
2019-10-04Neoverse N1 Errata Workaround 1542419laurenw-arm
2019-02-27Tegra: Support for scatterfile for the BL31 imageVarun Wadekar
2019-01-04Sanitise includes across codebaseAntonio Nino Diaz
2018-05-23Add support for dynamic mitigation for CVE-2018-3639Dimitris Papastamos
2018-05-23Rename symbols and files relating to CVE-2017-5715Dimitris Papastamos
2018-04-12Check presence of fix for errata 843419 in Cortex-A53Jonathan Wright
2018-03-14Fixup `SMCCC_ARCH_FEATURES` semanticsDimitris Papastamos
2018-01-18bl2-el3: Add BL2_EL3 imageRoberto Vargas
2017-05-24Use a callee-saved register to be AAPCS-compliantdp-arm
2017-05-03Use SPDX license identifiersdp-arm
2017-04-20Remove build option `ASM_ASSERTION`Antonio Nino Diaz
2017-03-20Add workaround for ARM Cortex-A53 erratum 855873Andre Przywara
2017-01-30Report errata workaround status to consoleJeenu Viswambharan
2017-01-24Use #ifdef for IMAGE_BL* instead of #ifMasahiro Yamada
2017-01-17Correct system include orderDavid Cunado
2016-12-15Add provision to extend CPU operations at more levelsJeenu Viswambharan
2016-03-22Make cpu operations warning a VERBOSE printSoby Mathew
2016-02-08Disable non-temporal hint on Cortex-A53/57Sandrine Bailleux
2015-04-08Add support to indicate size and end of assembly functionsKévin Petit
2015-03-13Initialise cpu ops after enabling data cacheVikram Kanigiri
2015-01-30Fix the Cortex-A57 reset handler register usageSoby Mathew
2015-01-26Call reset handlers upon BL3-1 entry.Yatharth Kochar
2015-01-13Invalidate the dcache after initializing cpu-opsSoby Mathew
2014-10-29Apply errata workarounds only when major/minor revisions match.Soby Mathew
2014-08-20Add CPU specific crash reporting handlersSoby Mathew
2014-08-20Add CPU specific power management operationsSoby Mathew
2014-08-20Add platform API for reset handlingSoby Mathew
2014-08-20Introduce framework for CPU specific operationsSoby Mathew
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