path: root/fmb_driver/fmb_hw.c

/**
*	@brief 		Hardware dependence part class for fmb Linux driver 
*	@since		2009/01/08 
*	@note		None
*	@attention	None
*	<B><I>COPYRIGHT FUJITSU LIMITED 2009</I></B>
*/

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

/****************************************************************************/
#include "fmb.h"
#include "fmb_core.h"
#include "fmb_api.h"

#ifndef VERSION
#define VERSION	"?.?.?.?"
#endif

/********************************************************/
/*					FUNCTION PROTOTYPE					*/
/********************************************************/

PREPARE_DEBUG();

MODULE_LICENSE( "GPL" );
MODULE_DESCRIPTION( "MB86_Driver" );
struct semaphore sm;

/********************************************************/
/*		GROBAL VALUES				*/
/********************************************************/
static struct fmb_hard_private 	s_Fmb_hard_private_list[FMB_MAX_CARDS];
static int						s_Fmb_cards_active = 0;
static int						s_Fmb_driver_version_major;
static spinlock_t				s_Fmb_hw_lock;
static dev_t s_dev;
/********************************************************/
/*							*/
/*	 register processing function		*/
/*							*/
/********************************************************/
/**
*	@brief		Register Read to DMA
*	@param[in]	priv_p			private data pointer
*	@param[in]	addr			DMA register address
*	@return		val				register read value
*	@note		None
*	@attention	None
*/  

unsigned long Fmb_hw_reg_read_dma(struct fmb_hard_private* priv_p, unsigned long addr)
{
	int				minor;
	unsigned long	val;
	
	minor = priv_p->minor;
	val = 0;
	
	MSG(DEBUG_LVL, minor, "START");
	
	if (!priv_p->dma_base) {
		MSG(INTERNAL_ERR_LVL, minor, "Address is not dma");
		return 0;
	}
	val = inl(priv_p->dma_base + addr);
	
	MSG(CODEC_LVL, minor, "read  BAR0 offset(0x%.2lx) = 0x%lx", addr, val);
	MSG(DEBUG_LVL, minor, "dma offset = 0x%lx", addr);
	MSG(DEBUG_LVL, minor, "END");
	return val;
}


/**
*	@brief		Register Write to DMA
*	@param[in]	priv_p			private data pointer
*	@param[in]	addr			DMA register address
*	@param[in]	data			register write value
*	@return		None
*	@note		None
*	@attention	None
*/  

void Fmb_hw_reg_write_dma(struct fmb_hard_private* priv_p, unsigned long addr, unsigned long data)
{
	int 			minor;
	minor = priv_p->minor;
	
	MSG(INTERNAL_FUNC, minor, "START");
	
	if (!priv_p->dma_base) {
		MSG(INTERNAL_ERR_LVL, minor, "Address is not dma");
		return;
	}
	outl(data, (priv_p->dma_base + addr));
	MSG(CODEC_LVL, minor, "write BAR0 offset(0x%.2lx) = 0x%lx", addr, data);
	MSG(DEBUG_LVL, minor, "dma offset = 0x%lx", addr);
	MSG(INTERNAL_FUNC, minor, "END");
}

/**
*	@brief		Register Read to LSI
*	@param[in]	priv_p			private data pointer
*	@param[in]	addr			LSI register address
*	@return		val				register read value
*	@note		None
*	@attention	None
*/  

unsigned short Fmb_hw_reg_read_lsi(struct fmb_hard_private* priv_p, unsigned long addr)
{
	int 			minor;
	int				retry;
	unsigned long	val;
	unsigned long	flags;
	unsigned long	intcsr;
	unsigned long	fRetryError;

	minor = priv_p->minor;
	retry = 5;
	val = 0;
	fRetryError = 0;
	
	MSG(INTERNAL_FUNC, minor, "START");
	
	spin_lock_irqsave(&priv_p->core_reg_lock, flags);
	if (!priv_p->core_base) {
		spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
		MSG(INTERNAL_ERR_LVL, minor, "Address is not core");
		return 0;
	}
	while (retry) {
		val = ioread32( (void*)(priv_p->core_base + (addr*2)) );
		MSG(CODEC_LVL, minor, "read  BAR1 offset(0x%.6lx) = 0x%lx", (addr*2), val);
		MSG(DEBUG_LVL, minor, "lsi offset = 0x%lx", addr);
		intcsr = Fmb_hw_reg_read_dma(priv_p, INTSOURCE);
											
		if (intcsr & 0x00000040) {
			Fmb_hw_reg_write_dma(priv_p, INTSOURCE, 0x00000040);
			fRetryError = 1;
			retry--;
			MSG(DEBUG_LVL, minor, "Target 256 Retry Error being checked");
			continue;
		}
	break;
	}
	spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
	MSG(INTERNAL_FUNC, minor, "END");
	return (unsigned short)val;
}



/**
*	@brief		Register Write to LSI
*	@param[in]	priv_p			private data pointer
*	@param[in]	addr			LSI register address
*	@param[in]	data			register write value
*	@return		None
*	@note		None
*	@attention	None
*/  

void Fmb_hw_reg_write_lsi(struct fmb_hard_private* priv_p, unsigned long addr, unsigned short data)
{
	int 			minor;
	int				retry;
	unsigned long	val;
	unsigned long	flags;
	unsigned long	intcsr;
	unsigned long	fRetryError;

	minor = priv_p->minor;
	retry = 5;
	val = 0;
	fRetryError = 0;
	
	MSG(DEBUG_LVL, minor, "START");
	
	spin_lock_irqsave(&priv_p->core_reg_lock, flags);
	val = (unsigned long)data;	
	if (!priv_p->core_base) {
		spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
		MSG(INTERNAL_ERR_LVL, minor, "Address is not core");
		return;
	}
	while (retry) {
		iowrite32((u32)data, (void*)(priv_p->core_base + (addr*2)) );
		MSG(CODEC_LVL, minor, "write BAR1 offset(0x%.6lx) = 0x%x", (addr*2), data);
		MSG(DEBUG_LVL, minor, "lsi offset = 0x%lx", addr);
		intcsr = Fmb_hw_reg_read_dma(priv_p, INTSOURCE);

		if (intcsr & 0x00000040) {
			Fmb_hw_reg_write_dma(priv_p, INTSOURCE, 0x00000040);
			fRetryError = 1;
			retry--;
			MSG(DEBUG_LVL, minor, "Target 256 Retry Error being checked");
			continue;
		}
		break;
	}
	spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
	MSG(DEBUG_LVL, minor, "END");
}


/**
*	@brief		Register Read to LSI Enhancing master
*	@param[in]	priv_p			private data pointer
*	@param[in]	addr			LSI Enhancing master register address
*	@return		val				register read value
*	@note		None
*	@attention	None
*/  

unsigned long Fmb_hw_reg_read_lsi_master(struct fmb_hard_private* priv_p, unsigned long addr)
{
	int				minor;
	int				retry;
	unsigned long	val;
	unsigned long	flags;
	unsigned long	intcsr;
	unsigned long	fRetryError;

	minor = priv_p->minor;
	retry = 5;
	val = 0;
	fRetryError = 0;
	
	MSG(INTERNAL_LOG, minor, "START");
	
	spin_lock_irqsave(&priv_p->core_reg_lock, flags);
	if (!priv_p->core_base) {
		spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
		MSG(INTERNAL_ERR_LVL, minor, "Address is not core");
		return 0;
	}
	while (retry) {
		val = ioread32( (void*)(priv_p->core_base + addr) );
		MSG(CODEC_LVL, minor, "read  BAR1 offset(0x%.6lx) = 0x%lx", addr, val);
		MSG(DEBUG_LVL, minor, "lsi offset = 0x%lx", addr);
		intcsr = Fmb_hw_reg_read_dma(priv_p, INTSOURCE);	

		if (intcsr & 0x00000040) {
			Fmb_hw_reg_write_dma(priv_p, INTSOURCE, 0x00000040);
			fRetryError = 1;
			retry--;
			MSG(DEBUG_LVL, minor, "Target 256 Retry Error being checked");
			continue;
		}
	break;
	}
	spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
	MSG(INTERNAL_LOG, minor, "END");
	return val;
}


/**
*	@brief		Register Write to LSI Enhancing master
*	@param[in]	priv_p			private data pointer
*	@param[in]	addr			LSI Enhancing master register address
*	@param[in]	data			register write value
*	@return		None
*	@note		None
*	@attention	None
*/  

void Fmb_hw_reg_write_lsi_master(struct fmb_hard_private* priv_p, unsigned long addr, unsigned long data)
{
	int 			minor;
	int				retry;
	unsigned long	flags;
	unsigned long	intcsr;
	unsigned long	fRetryError;

	minor = priv_p->minor;
	retry = 5;
	fRetryError = 0;
	
	MSG(INTERNAL_LOG, minor, "START");
	
	spin_lock_irqsave(&priv_p->core_reg_lock, flags);
	if (!priv_p->core_base) {
		spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
		MSG(INTERNAL_ERR_LVL, minor, "Address is not core");
		return;
	}
	while (retry) {
		iowrite32((u32)data, (void*)(priv_p->core_base + addr) );
		MSG(CODEC_LVL, minor, "write BAR1 offset(0x%.6lx) = 0x%lx", addr, data);
		MSG(DEBUG_LVL, minor, "lsi offset = 0x%lx", addr);
		intcsr = Fmb_hw_reg_read_dma(priv_p, INTSOURCE);
		
		if (intcsr & 0x00000040) {
			Fmb_hw_reg_write_dma(priv_p, INTSOURCE, 0x00000040);
			fRetryError = 1;
			retry--;
			MSG(DEBUG_LVL, minor, "Target 256 Retry Error being checked");
			continue;
		}
		break;
	}
	spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
	MSG(INTERNAL_LOG, minor, "END");
}

/**
*	@brief		Register Read Modfi Write to LSI
*	@param[in]	priv_p			private data pointer
*	@param[in]	addr			LSI register address
*	@param[in]	shift			shift value at the time of writing
*	@param[in]	mask			mask value at the time of writing
*	@param[in]	data			register write value
*	@return		val				register read value
*	@note		None
*	@attention	None
*/

unsigned short Fmb_hw_reg_rmw_lsi(struct fmb_hard_private* priv_p, unsigned long addr, unsigned short shift,
					      unsigned short mask, unsigned short data)
{
	int				minor;
	int				retry;
	unsigned long	val;
	unsigned long	intcsr;
	unsigned long	flags;
	unsigned long	shift_tmp;
	unsigned long	mask_tmp;
	unsigned long	data_tmp;
	unsigned long	fRetryError;

	minor = priv_p->minor;
	retry = 5;
	shift_tmp = 0;
	mask_tmp = 0;
	data_tmp = 0;
	fRetryError = 0;
	
	MSG(INTERNAL_FUNC, minor, "START");

	spin_lock_irqsave(&priv_p->core_reg_lock, flags);
	shift_tmp = (unsigned long)shift;
	mask_tmp = (unsigned long)mask;
	data_tmp = (unsigned long)data;
	
	if (!priv_p->core_base) {
		spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
		MSG(INTERNAL_ERR_LVL, minor, "Address is not core");
		return 0;
	}
	while (retry) {
		val = ioread32( (void*)(priv_p->core_base + (addr*2)) );
		MSG(CODEC_LVL, minor, "read  BAR1 offset(0x%.6lx) = 0x%lx", (addr*2), val);
		val &= ~(mask_tmp << shift_tmp);					/* clear pertinent bit */
		val |= ((data_tmp & mask_tmp) << shift_tmp);			/* set pertinent bit */
		iowrite32((u32)val, (void*)(priv_p->core_base + (addr*2)) );
		MSG(CODEC_LVL, minor, "write BAR1 offset(0x%.6lx) = 0x%lx", (addr*2), val);
		MSG(DEBUG_LVL, minor, "lsi offset = 0x%lx", addr);
		intcsr = Fmb_hw_reg_read_dma(priv_p, INTSOURCE);
		
		if (intcsr & 0x00000040) {
			Fmb_hw_reg_write_dma(priv_p, INTSOURCE, 0x00000040);
			fRetryError = 1;
			retry--;
			MSG(DEBUG_LVL, minor, "Target 256 Retry Error being checked");
			continue;
		}
	break;
	}
	spin_unlock_irqrestore(&priv_p->core_reg_lock, flags);
	MSG(INTERNAL_FUNC, minor, "END");
	return (unsigned short)val;
}

/**
*	@brief	Check access area for lsi
*	@param[in]	priv_p			private data pointer
*	@param[in]	offset_addr		offset address to specified PCI
*	@param[in]	access_size		Size of access area
*	@return		0				Normal end
*	@return		-EINVAL			The content of the parameter is illegal.
*	@note		None
*	@attention	None
*/

int Fmb_hw_check_addr_lsi(struct fmb_hard_private* priv_p, unsigned long offset_addr, unsigned long access_size)
{
	int				minor;
	unsigned long	tail_addr;

	minor = priv_p->minor;

	MSG(INTERNAL_FUNC, minor, "START");

	tail_addr = (offset_addr + access_size)*2;
	if ((offset_addr*2) > FMB_CORE_LSI_SIZE) {
		MSG(INTERNAL_ERR_LVL, minor, "Specified address is abnormal.");
		return -EINVAL;
	}
	if (tail_addr > FMB_CORE_LSI_SIZE) {
		MSG(INTERNAL_ERR_LVL, minor, "Specified address is abnormal.");
		return -EINVAL;
	}
	MSG(INTERNAL_FUNC, minor, "END");
	return 0;
}


/**
*   @brief	Check access area for PCI 
*	@param[in]	priv_p			private data pointer
*   @param[in]	pci_type		Type of specified PCI (Not used)
*   @param[in]	offset_addr		offset address to specified PCI
*   @param[in]	access_size		Size of access area
*   @return		0				Normal end
*   @return		-EINVAL			The content of the parameter is illegal.
*   @note		None
*   @attention	None
*/

int Fmb_hw_check_addr_pci(struct fmb_hard_private* priv_p, unsigned long pci_type, unsigned long offset_addr, 
				unsigned long access_size)
{
	int 			minor;
	unsigned long	tail_addr;

	minor = priv_p->minor;

	MSG(INTERNAL_LOG, minor, "START");

	tail_addr = offset_addr + access_size;
	switch (pci_type){
		case FMB_TYPE_DMA:
			if (offset_addr >= FMB_DMA_SIZE) {
				MSG(INTERNAL_ERR_LVL, minor, "Specified address is abnormal.");
				return -EINVAL;
			}
			if (tail_addr >= FMB_DMA_SIZE) {
				MSG(INTERNAL_ERR_LVL, minor, "Specified address is abnormal.");
				return -EINVAL;
			}
			break;
		case FMB_TYPE_LSI:
			if (offset_addr < 0x1E0000){
				MSG(INTERNAL_ERR_LVL, minor, "Specified address is abnormal.");
				return -EINVAL;
			}
			if (offset_addr >= FMB_CORE_SIZE) {
				MSG(INTERNAL_ERR_LVL, minor, "Specified address is abnormal.");
				return -EINVAL;
			}
			if (tail_addr >= FMB_CORE_SIZE) {
				MSG(INTERNAL_ERR_LVL, minor, "Specified address is abnormal.");
				return -EINVAL;
			}
			break;
		default:
			MSG(INTERNAL_ERR_LVL, minor, "invalid type");
			return -EINVAL;
	}
	MSG(INTERNAL_LOG, minor, "END");
	return 0;
}

/********************************************************/
/*							*/
/*	PCI(Interrupt) processing function			*/
/*							*/
/********************************************************/
/**
*	@brief		DMA/LSI Clear Interrupt 
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

void Fmb_hw_clear_irq(struct fmb_hard_private* priv_p )
{
	int 			minor;
	unsigned long	imask;
	unsigned long	intcsr;
	unsigned long	dmacsr;
	unsigned long	fpciintst;
	unsigned short	irqst; 

	minor = priv_p->minor;

	MSG(CODEC_FUNC, minor, "START");
	MSG(INTERNAL_FUNC, minor, "START");

	local_irq_save(imask);
	local_irq_disable();

	intcsr = Fmb_hw_reg_read_dma(priv_p, INTSOURCE);

	if (intcsr & 0x00000010) {
		/* DMA ch0 */
		dmacsr = Fmb_hw_reg_read_dma(priv_p, DMA0CMDSTS);
		dmacsr |= 0x8;
		Fmb_hw_reg_write_dma(priv_p, DMA0CMDSTS, dmacsr);
		MSG(DEBUG_LVL, minor, "DMA ch0 clear");
	}

	if (intcsr & 0x00000020) {
		/* DMA ch1 */
		dmacsr = Fmb_hw_reg_read_dma(priv_p, DMA1CMDSTS);
		dmacsr |= 0x8;
		Fmb_hw_reg_write_dma(priv_p, DMA1CMDSTS, dmacsr);
		MSG(DEBUG_LVL, minor, "DMA ch1 clear");
	}

	if (intcsr & 0x00000001) {
		/* LXINT */
		fpciintst = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTST);

		if (fpciintst & FPCI_INTMASK_INT) {
			irqst = Fmb_hw_reg_read_lsi(priv_p, FMB_API_IRQST_ALL);

			irqst &= (API_IRQST_TCPU_CMD | API_IRQST_TACK_CMD | API_IRQST_VSYNC_CMD);
			Fmb_hw_reg_write_lsi(priv_p, FMB_API_IRQST_ALL, irqst);
			MSG(DEBUG_LVL, minor, "INT clear");
		}
		Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTST, fpciintst);
		MSG(DEBUG_LVL, minor, "LXINT clear");
	}
	local_irq_restore(imask);
	local_irq_enable();
	MSG(INTERNAL_FUNC, minor, "END");
	MSG(CODEC_FUNC, minor, "END");
}


/**
*	@brief		DMA/LSI Enable Interrupt 
*	@param[in]	priv_p			private data pointer
*	@param[in]	irq_type		irq type
*	@return		None
*	@note		None
*	@attention	None
*/

void Fmb_hw_enable_irq(struct fmb_hard_private* priv_p, int irq_type )
{
	int				minor;
	unsigned long	val;
	unsigned long	flags;

	minor = priv_p->minor;
	val = 0;

	MSG(CODEC_FUNC, minor, "START");
	MSG(INTERNAL_FUNC, minor, "START");

	switch (irq_type) {
		/* DMA */
		case IRQ_FMB_DMA:
			spin_lock_irqsave(&priv_p->dma_reg_lock, flags);
			val = Fmb_hw_reg_read_dma(priv_p, INTENABLE);
			val |= 0x00000031;
			Fmb_hw_reg_write_dma(priv_p, INTENABLE, val);
			spin_unlock_irqrestore(&priv_p->dma_reg_lock, flags);
			MSG(DEBUG_LVL, minor, "DMA enable");
			break;
		
		/* LSI */		
		/* INT */
		case IRQ_FMB_INT:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val |= FPCI_INTMASK_INT;
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			Fmb_hw_reg_write_lsi(priv_p, FMB_API_HCPU_IRQEN_TCPU, API_IRQST_TCPU_CMD | API_IRQST_TACK_CMD | API_IRQST_VSYNC_CMD);
			MSG(DEBUG_LVL, minor, "INT enable");
			break;
		
		/* XERROR */
		case IRQ_FMB_XERROR:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val |= 0x80000000;
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			MSG(DEBUG_LVL, minor, "XERROR enable");
			break;

		/* EDERR */
		case IRQ_FMB_EDERR:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val |= 0x00400000;
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			MSG(DEBUG_LVL, minor, "EDERR enable");
			break;

		/* DDERR */
		case IRQ_FMB_DDERR:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val |= 0x00040000;
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			MSG(DEBUG_LVL, minor, "DDERR enable");
			break;

		default:
			break;
	}
	MSG(INTERNAL_FUNC, minor, "END");
	MSG(CODEC_FUNC, minor, "END");
}

/**
*	@brief		DMA/LSI Disable Interrupt Vector
*	@param[in]	priv_p			private data pointer
*	@param[in]	irq_type		irq type
*	@return		None
*	@note		None
*	@attention	None
*/

void Fmb_hw_disable_irq(struct fmb_hard_private* priv_p, int irq_type)
{
	int 			minor;
	unsigned long	val;
	unsigned long	flags;
	
	minor = priv_p->minor;
	val = 0;

	MSG(CODEC_FUNC, minor, "START");
	MSG(INTERNAL_FUNC, minor, "START");

	switch (irq_type) {
		/* DMA */
		case IRQ_FMB_DMA:
			spin_lock_irqsave(&priv_p->dma_reg_lock, flags);
			val = Fmb_hw_reg_read_dma(priv_p, INTENABLE);
			val &= ~(0x00000030);
			Fmb_hw_reg_write_dma(priv_p, INTENABLE, val);
			spin_unlock_irqrestore(&priv_p->dma_reg_lock, flags);
			MSG(DEBUG_LVL, minor, "DMA disable");
			break;
		
		/* LSI */
		/* INT */
		case IRQ_FMB_INT:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val &= ~(FPCI_INTMASK_INT);
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			Fmb_hw_reg_write_lsi(priv_p, FMB_API_HCPU_IRQEN_TCPU, 0x0000);
			MSG(DEBUG_LVL, minor, "INT disable");
			break;
		
		/* XERROR */
		case IRQ_FMB_XERROR:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val &= ~(0x80000000);		
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			MSG(DEBUG_LVL, minor, "XERROR disable");
			break;

		/* EDERR */
		case IRQ_FMB_EDERR:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val &= ~(0x00400000);		
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			MSG(DEBUG_LVL, minor, "EDERR disable");
			break;

		/* DDERR */
		case IRQ_FMB_DDERR:
			val = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTEN);
			val &= ~(0x00040000);		
			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTEN, val);
			MSG(DEBUG_LVL, minor, "DDERR disable");
			break;

		default:
			break;
	}
	MSG(INTERNAL_FUNC, minor, "END");
	MSG(CODEC_FUNC, minor, "END");
}

/**
*	@brief		FMB Hardware interrupt initialize
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

static void fmb_hw_irq_init(struct fmb_hard_private*	priv_p)
{
	int			minor;
	
	minor = priv_p->minor;
	
	MSG(INTERNAL_LOG, minor, "START");
	
	Fmb_hw_disable_irq(priv_p, IRQ_FMB_DMA);
	Fmb_hw_disable_irq(priv_p, IRQ_FMB_INT);
	Fmb_hw_disable_irq(priv_p, IRQ_FMB_XERROR);
	Fmb_hw_disable_irq(priv_p, IRQ_FMB_EDERR);
	Fmb_hw_disable_irq(priv_p, IRQ_FMB_DDERR);

	MSG(INTERNAL_LOG, minor, "END");
}

/********************************************************/
/*							*/
/*	Hardware dependence initialization function	*/
/*							*/
/********************************************************/

/**
*	@brief		FMB Hardware PCI Memory mapping
*	@param[in]	priv_p			private data pointer
*	@return		0				normal end
*	@note		None
*	@attention	None
*/

static int fmb_hw_memmap(struct fmb_hard_private*	priv_p)
{
	int 			minor;
	unsigned long	phyaddr;

	minor = priv_p->minor;

	MSG(INTERNAL_LOG, minor, "START");
		
	/* BAR0 */
	if (!request_region(pci_resource_start(priv_p->pci_dev_p, 0),	
		pci_resource_len(priv_p->pci_dev_p, 0), FMB_DRIVER_NAME))
	{
		MSG(KERN_ERR_LVL, minor, "Cannot reserve I/O ports(BAR0)");
		goto err_out_disable;
	}
	priv_p->dma_base = pci_resource_start(priv_p->pci_dev_p, 0);
	MSG(DEBUG_LVL, minor, "Reservation success I/O ports(BAR0)");
	
	/* BAR1 */
	if (!request_mem_region(pci_resource_start(priv_p->pci_dev_p, 1),
							pci_resource_len(priv_p->pci_dev_p, 1), FMB_DRIVER_NAME))
	{
		MSG(KERN_ERR_LVL, minor, "Cannot reserve MMIO region(BAR1)");
		goto err_out_free_pio_region;
	}
	phyaddr                = pci_resource_start(priv_p->pci_dev_p, 1);
	priv_p->core_base     = (unsigned long)ioremap(phyaddr,FMB_CORE_SIZE);
	MSG(DEBUG_LVL, minor, "Reservation success MMIO region(BAR1)");

	MSG(RESOURCE_LVL, minor, "# address map");
	MSG(RESOURCE_LVL, minor, "# FMB DMA : L:0x%lx",
		priv_p->dma_base);

	MSG(RESOURCE_LVL, minor, "# FMB LSI : L:0x%lx S:0x%08x",
		priv_p->core_base,
		FMB_CORE_SIZE);

	MSG(INTERNAL_LOG, minor, "END");	
	return 0;

err_out_disable:
	pci_disable_device(priv_p->pci_dev_p);
	return -1;
err_out_free_pio_region:
	release_region(pci_resource_start(priv_p->pci_dev_p, 0), pci_resource_len(priv_p->pci_dev_p, 0));
	return -1;
}

/**
*	@brief		FMB Hardware PCI UnMemory mapping
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

static void fmb_hw_unmemmap(struct fmb_hard_private* priv_p)
{
	int				minor;

	minor = priv_p->minor;

	MSG(INTERNAL_LOG, minor, "START");

	/* BAR1 */
	iounmap((void*)priv_p->core_base);
	release_mem_region(pci_resource_start(priv_p->pci_dev_p, 1), pci_resource_len(priv_p->pci_dev_p, 1));
	/* BAR0 */
	release_region(pci_resource_start(priv_p->pci_dev_p, 0), pci_resource_len(priv_p->pci_dev_p, 0));
	
	MSG(INTERNAL_LOG, minor, "END");
}

/**
*	@brief		FMB Codec Lsi Initialize
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

void Fmb_hw_codec_lsi_init(struct fmb_hard_private* priv_p)
{
	int				minor;
	
	minor = priv_p->minor;

	MSG(CODEC_FUNC, minor, "START");
	MSG(INTERNAL_FUNC, minor, "START");

    Fmb_hw_reg_write_lsi_master(priv_p, FPCI_CNT, 0x00000003);

    mdelay(FMB_CARD_RESET_DELAY_TIME1);                         /* wait 1ms */

    Fmb_hw_reg_write_lsi_master(priv_p, FPCI_CNT, 0x00000002);

    mdelay(FMB_CARD_RESET_DELAY_TIME1);                         /* wait 1ms */

    Fmb_hw_reg_write_lsi_master(priv_p, FPCI_CODEC_CNT, 0x00000000);

    mdelay(FMB_CARD_RESET_DELAY_TIME1);                         /* wait 1ms */

    Fmb_hw_reg_write_lsi_master(priv_p, FPCI_CODEC_CNT, 0x00000002);

    mdelay(FMB_CARD_RESET_DELAY_TIME1);                         /* wait 1ms */

    Fmb_hw_reg_write_lsi_master(priv_p, FPCI_CODEC_CNT, 0x00000003);

    mdelay(FMB_CARD_RESET_DELAY_TIME2);             /* wait 500ms */


	MSG(INTERNAL_FUNC, minor, "END");
	MSG(CODEC_FUNC, minor, "END");
}

/**
*	@brief  PCI Card Reset
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

static void fmb_card_reset(struct fmb_hard_private* priv_p)
{
	int				minor;
	
	minor = priv_p->minor;

	MSG(CODEC_FUNC, minor, "START");
	MSG(INTERNAL_LOG, minor, "START");
	
	Fmb_hw_reg_write_dma(priv_p, INTENABLE, 0x00000000);
	Fmb_hw_reg_write_dma(priv_p, TCSTATUS,  0x80000000);
	Fmb_hw_reg_write_dma(priv_p, INTSOURCE, 0x000000C0);
	Fmb_hw_reg_write_dma(priv_p, TCSTATUS,  0x80000000);
	Fmb_hw_reg_write_dma(priv_p, INTSOURCE, 0x000000C0);

	Fmb_hw_reg_write_dma(priv_p, DMA0CMDSTS, 0x00000704);
	Fmb_hw_reg_write_dma(priv_p, DMA0CMDSTS, 0x00000708);
	Fmb_hw_reg_write_dma(priv_p, DMA0CMDSTS, 0x00000700);
	Fmb_hw_reg_write_dma(priv_p, DMA1CMDSTS, 0x00000604);
	Fmb_hw_reg_write_dma(priv_p, DMA1CMDSTS, 0x00000608);
	Fmb_hw_reg_write_dma(priv_p, DMA1CMDSTS, 0x00000600);

	MSG(INTERNAL_LOG, minor, "END");
	MSG(CODEC_FUNC, minor, "END");
}


/**
*	@brief  PCI Card Powerdown
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

static void fmb_card_powerdown( struct fmb_hard_private* priv_p)
{
	int				minor;
	
	minor = priv_p->minor;

	MSG(CODEC_FUNC, minor, "START");
	MSG(INTERNAL_LOG, minor, "START");
	
	Fmb_hw_reg_write_dma(priv_p, INTENABLE, 0x00000000);
	Fmb_hw_reg_write_lsi_master(priv_p, FPCI_CODEC_CNT, 0x00000000);
	Fmb_hw_reg_write_lsi_master(priv_p, FPCI_CNT,0x00000000);

	MSG(INTERNAL_LOG, minor, "END");
	MSG(CODEC_FUNC, minor, "END");
}


/**
*	@brief		FMB Hardware Private Data initialize
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

static void fmb_hw_private_data_init(struct fmb_hard_private* priv_p)
{
	int 			minor;
	unsigned char	pci_latency;

	minor = priv_p->minor;

	MSG(INTERNAL_LOG, minor, "START");

	spin_lock_init(&priv_p->lock_hw_priv);
	spin_lock_init(&priv_p->dma_reg_lock);
	spin_lock_init(&priv_p->core_reg_lock);

	pci_read_config_byte(priv_p->pci_dev_p, PCI_CLASS_REVISION, &priv_p->card_rev);
	pci_read_config_byte(priv_p->pci_dev_p, PCI_LATENCY_TIMER, &pci_latency);

	/* init poll waitqueue */
	init_waitqueue_head(&priv_p->poll_waitq);

	MSG(INTERNAL_LOG, minor, "END");
}

/**
*	@brief		FMB  Hardware Private Data release
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*/

static void fmb_hw_private_data_release(struct fmb_hard_private* priv_p)
{
	int 			minor;
	
	minor = priv_p->minor;

	MSG(INTERNAL_LOG, minor, "START");
	
	/* initialize the core private data */
	memset( &s_Fmb_hard_private_list[minor], 0, sizeof(struct fmb_hard_private));
	s_Fmb_hard_private_list[minor].minor = -1;

	MSG(INTERNAL_LOG, minor, "END");
}

/********************************************************/
/*	systemcall basic API Function			*/
/********************************************************/

/**
*	@brief		FMB system call open()
*	@param[in]	*ip			Information in filesystem
*	@param[in]	*fp			File pointer
*	@return		0
*	@note		None
*	@attention	None
*/

static int fmb_hw_open(struct inode* ip_p, struct file* fp_p)
{
	int 			minor;
	
	minor = MINOR(ip_p->i_rdev);		

	MSG(DRIVER_FUNC_LVL, minor, "START");
	
	
	fp_p->private_data = &s_Fmb_hard_private_list[minor];	
	
	MSG(DRIVER_FUNC_LVL, minor, "END");
	return 0;
}


/**
*	@brief		FMB system call close()
*	@param[in]	*ip			Information in filesystem
*	@param[in]	*fp			File pointer
*	@return		0
*	@note		None
*	@attention	None
*/

static int fmb_hw_release(struct inode* ip_p, struct file* fp_p)
{
	int 			minor;
	struct fmb_hard_private*	priv_p = (struct fmb_hard_private*)fp_p->private_data;

	minor = priv_p->minor;

	MSG(DRIVER_FUNC_LVL, minor, "START");
	MSG(DRIVER_FUNC_LVL, minor, "END");
	return 0;
}

/**
*	@brief		FMB system call read()
*	@param[in]		*fp				File pointer
*	@param[in,out]	*buffp			Data pointer
*	@param[in]		len				Data length
*	@param[in]		*offset			Object pointer
*	@return			0
*	@note			None
*	@attention		None
*/

static ssize_t fmb_hw_read(struct file* fp, char __user* buffp_p, size_t len, loff_t* offset_p)
{
	int 			minor;
	int				rc;
	struct fmb_hard_private*	priv_p = (struct fmb_hard_private*)fp->private_data;

	minor = priv_p->minor;
	
	MSG(DRIVER_FUNC_LVL, minor, "START");

	rc = Fmb_api_read(priv_p, fp, buffp_p, len, offset_p);		
	MSG(DRIVER_FUNC_LVL, minor, "END");
	return rc;
}

/**
*	@brief		FMB system call write()
*	@param[in]		*fp				File pointer
*	@param[in,out]	*buffp			Data pointer
*	@param[in]		len				Data length
*	@param[in]		*offset			Object pointer
*	@return			0
*	@note			None
*	@attention		None
*/

static ssize_t fmb_hw_write(struct file* fp, const char __user* buffp_p, size_t len, loff_t* offset_p)
{
	int 			minor;
	int				rc;	
	struct fmb_hard_private*	priv_p = (struct fmb_hard_private*)fp->private_data;
	
	minor = priv_p->minor;
	
	MSG(DRIVER_FUNC_LVL, minor, "START");

	rc = Fmb_api_write(priv_p, fp, buffp_p, len, offset_p);
	MSG(DRIVER_FUNC_LVL, minor, "END");
	return rc;
}

/**
*	@brief		FMB system call poll()
*	@param[in]		*fp		File pointer
*	@param[in,out]	*pt		File poll table
*	@return			0
*	@note			None
*	@attention		None
*/

static unsigned int fmb_hw_poll(struct file* fp_p, poll_table* pt_p)
{
	int 			minor;
	int				rc;
	struct fmb_hard_private*	priv_p = (struct fmb_hard_private*)fp_p->private_data;

	minor = priv_p->minor;
	rc = 0;
	
	MSG(DRIVER_FUNC_LVL, minor, "START");

	poll_wait(fp_p, &priv_p->poll_waitq, pt_p);

	if (Fmb_core_get_factor_num(priv_p->core_priv_p)) {
		/** factor info get active */ 
		MSG(DEBUG_LVL, minor, "factor info get active");
		rc = POLLPRI;
	}
	MSG(DRIVER_FUNC_LVL, minor, "END");
	return rc;
}

/**
*	@brief		FMB system call ioctl()
*	@param[in]	*ip		Information in filesystem
*	@param[in]	*fp		File pointer
*	@param[in]	cmd		Command number from application
*	@param[in]	arg		Argument from application 
*	@return		0
*	@note		None
*	@attention	None
*/

static long fmb_hw_ioctl(struct file* fp_p,
			 unsigned int cmd, unsigned long arg)
{
	int 			minor;
	int				rc;	
	struct fmb_hard_private*	priv_p = (struct fmb_hard_private*)fp_p->private_data;

	minor = priv_p->minor;
	rc = 0;
	
	MSG(DRIVER_FUNC_LVL, minor, "cmd:0x%x,START", cmd);

	/* ioctl() to FMB Codec */ 
	rc = Fmb_api_ioctl(priv_p, cmd, arg);

	MSG(DRIVER_FUNC_LVL, minor, "cmd:0x%x,END", cmd);
	return rc;
}

/********************************************************/
/*							*/
/*	Hardware dependence Interrupt process function	*/
/*							*/
/********************************************************/

/**
*	@brief		FMB Hardware interrupt
*	@param[in]	irq			Interruption number
*	@param[in]	*dev_id		device id
*	@param[in]	*regs		Pointer of register information
*	@return		IRQ_HANDLED	Normal end
*	@note		None
*	@attention	None
*/

static irqreturn_t fmb_hw_interrupt(int irq, void *dev_id)
{
	int				minor;
	int				dma0Int;
	int				dma1Int;	
	unsigned long	intcsr;
	unsigned long	dmacsr;
	unsigned long	fpciintst;
	struct fmb_hard_private* priv_p = (struct fmb_hard_private*)dev_id;
	
	dma0Int      = 0;
	dma1Int      = 0;

	minor = priv_p->minor;
	
	MSG(CODEC_FUNC, minor, "START");
	MSG(DRIVER_FUNC_LVL, minor, "START");

	intcsr = Fmb_hw_reg_read_dma(priv_p, INTSOURCE);

	if (intcsr & 0x00000010) {
		/* DMA ch0 interrrupt */
		MSG(DMA0MSG_LVL, minor, "DMA ch0 interrrupt message");

		dmacsr = Fmb_hw_reg_read_dma(priv_p, DMA0CMDSTS);
		dmacsr |= 0x8;
		Fmb_hw_reg_write_dma(priv_p, DMA0CMDSTS, dmacsr);
		dma0Int = 1;

		MSG(DRIVER_FUNC_LVL, minor, "DMA ch0 interrrupt Registration");
	}

	if (intcsr & 0x00000020) {
		/* DMA ch1 interrrupt */
		MSG(DMA1MSG_LVL, minor, "DMA ch1 interrrupt message");

		dmacsr = Fmb_hw_reg_read_dma(priv_p, DMA1CMDSTS);
		dmacsr |= 0x8;
		Fmb_hw_reg_write_dma(priv_p, DMA1CMDSTS, dmacsr);
		dma1Int = 1;

		MSG(DRIVER_FUNC_LVL, minor, "DMA ch1 interrrupt Registration");
	}

	if (intcsr & 0x00000001) {
		/* LXINT */
		fpciintst = Fmb_hw_reg_read_lsi_master(priv_p, FPCI_INTST);	
			if (fpciintst & FPCI_INTMASK_XERROR ){
				Fmb_core_xerror_irq(priv_p->core_priv_p);

				MSG(DRIVER_FUNC_LVL, minor, "XERROR interrrupt Registration");
			}
		
			if(fpciintst & FPCI_INTMASK_INT ){

				Fmb_core_int_irq(priv_p->core_priv_p);
				MSG(DRIVER_FUNC_LVL, minor, "INT interrrupt Registration");
			}

			if(fpciintst & FPCI_INTMASK_EDERR ){

				Fmb_core_ederr_irq(priv_p->core_priv_p);
				MSG(DRIVER_FUNC_LVL, minor, "EDERR interrrupt Registration");
			}

			if(fpciintst & FPCI_INTMASK_DDERR ){

				Fmb_core_dderr_irq(priv_p->core_priv_p);
				MSG(DRIVER_FUNC_LVL, minor, "DDERR interrrupt Registration");
			}

			Fmb_hw_reg_write_lsi_master(priv_p, FPCI_INTST, fpciintst);
			MSG(DRIVER_FUNC_LVL, minor, "LXINT interrrupt Registration");
		}
	
	if (dma0Int) {
		Fmb_core_dma_rcv_irq(priv_p->core_priv_p);
		MSG(DRIVER_FUNC_LVL, minor, "DMA forwarding interrupt for reception");
	}

	if (dma1Int) {
		Fmb_core_dma_snd_irq(priv_p->core_priv_p);
		MSG(DRIVER_FUNC_LVL, minor, "DMA forwarding interrupt for transmission");
	}

	MSG(DRIVER_FUNC_LVL, minor, "END");
	MSG(CODEC_FUNC, minor, "END");
	return IRQ_HANDLED;
}


/**
*	@brief		FMB Hardware interrupt set
*	@param[in]	priv_p			private data pointer
*	@return		None
*	@note		None
*	@attention	None
*
*/

void Fmb_hw_interrupt_set(struct fmb_hard_private* priv_p)
{
	int 			minor;
	int				result;
	
	minor = priv_p->minor;

	MSG(INTERNAL_FUNC, minor, "START");

	result = request_irq(priv_p->pci_dev_p->irq, fmb_hw_interrupt,
			   IRQF_DISABLED | IRQF_SHARED, FMB_DRIVER_NAME, (void *)priv_p);
	if(result < 0) {
		Fmb_core_remove(priv_p->core_priv_p);	
		fmb_hw_unmemmap(priv_p);			
		pci_disable_device(priv_p->pci_dev_p);			
		cdev_del(&priv_p->cdev_info);				
		MSG(KERN_ERR_LVL, minor, "Can not fmb_hw_interrupt reuest");
	}else if(result == 0){
		MSG(DEBUG_LVL, minor, "interrupt Handler Registration");
	}

	MSG(INTERNAL_FUNC, minor, "END");
}


/********************************************************/
/*							*/
/*	Driver module initialization function		*/
/*							*/
/********************************************************/
/*------------------------------------------------------*/
/* Data for driver registration                 */
/*------------------------------------------------------*/
static struct file_operations fmb_fops =
{
	.owner		=	THIS_MODULE,
	.read		=	fmb_hw_read,
	.write		=	fmb_hw_write,
	.poll		=	fmb_hw_poll,
	.unlocked_ioctl	=	fmb_hw_ioctl,
	.open		=	fmb_hw_open,
	.release	=	fmb_hw_release,
};


/**
*	@brief		FMB system call probe()
*	@param[in]	dev			pci device Structure pointer
*	@param[in]	pci_id		pci device id pointer
*	@return		0
*	@note		None
*	@attention	None
*/

static int __devinit fmb_hw_probe(struct pci_dev* pci_p, const struct pci_device_id* pci_id_p)
{
	
	int 			minor;
	int				result;
	struct fmb_hard_private*	priv_p;
	unsigned long	flags;
	dev_t dev;
	
	minor = -1;
	
	MSG(DRIVER_FUNC_LVL, minor, "START");
	
	result = pci_enable_device(pci_p);
	if(result != 0){
		MSG(KERN_ERR_LVL, minor, "pci device enable error");
		return -ENODEV;
	}

	spin_lock_irqsave(&s_Fmb_hw_lock, flags);	
	if (s_Fmb_cards_active == FMB_MAX_CARDS) {
		spin_unlock_irq(&s_Fmb_hw_lock);					
		pci_disable_device(pci_p);							
		MSG(INTERNAL_ERR_LVL, minor, "No remainder of private data.");
		return -ENOMEM;
	}

	priv_p = &s_Fmb_hard_private_list[s_Fmb_cards_active];

	priv_p->pci_dev_p = pci_p;
	priv_p->minor = FMB_MINOR_NUM_START + s_Fmb_cards_active;
	s_Fmb_cards_active++;
	
	minor = priv_p->minor;
	
	spin_unlock_irqrestore(&s_Fmb_hw_lock, flags);		

	fmb_hw_private_data_init(priv_p);		
	result = fmb_hw_memmap(priv_p);					
	if(result < 0){
		MSG(INTERNAL_ERR_LVL, minor, "memmap error");
		return -ENOMEM;
	}
	
	pci_set_master(priv_p->pci_dev_p);					
	pci_set_drvdata(priv_p->pci_dev_p,priv_p);

	fmb_card_powerdown(priv_p);			
	fmb_card_reset(priv_p);				

	result = Fmb_core_probe(priv_p);
	if(result < 0){
		fmb_hw_unmemmap(priv_p);			
		pci_disable_device(priv_p->pci_dev_p);
		MSG(INTERNAL_ERR_LVL, minor, "core_probe error");
		return -ENOMEM;
	}		

	Fmb_hw_codec_lsi_init(priv_p);		
	fmb_hw_irq_init(priv_p);			

	dev = MKDEV(s_Fmb_driver_version_major, minor);
	cdev_init(&priv_p->cdev_info, &fmb_fops);		
	priv_p->cdev_info.owner	= THIS_MODULE;
	priv_p->cdev_info.ops	= &fmb_fops;
	result = cdev_add(&priv_p->cdev_info, dev, 1);		
	if(result < 0) {
		Fmb_core_remove(priv_p->core_priv_p);	
		fmb_hw_unmemmap(priv_p);				
		pci_disable_device(priv_p->pci_dev_p);
		MSG(KERN_ERR_LVL, minor, "Can not module:fmb_driver registe");
		return -EBUSY;
	}
		
	result = request_irq(priv_p->pci_dev_p->irq, fmb_hw_interrupt,
			   IRQF_DISABLED | IRQF_SHARED, FMB_DRIVER_NAME, (void *)priv_p);
	if(result < 0) {
		Fmb_core_remove(priv_p->core_priv_p);	
		fmb_hw_unmemmap(priv_p);			
		pci_disable_device(pci_p);			
		cdev_del(&priv_p->cdev_info);				
		MSG(KERN_ERR_LVL, minor, "Can not fmb_hw_interrupt reuest");
		return -EBUSY;
	}else if(result == 0){
		MSG(DEBUG_LVL, minor, "interrupt Handler Registration");
	}	
	
	MSG(RESOURCE_LVL, minor, "Driver Version:(%s)\n", VERSION);
	MSG(DRIVER_FUNC_LVL, minor, "END");
	return 0;
}

/**
*	@brief		FMB system call remove()
*	@param[in]	dev		pci device Structure pointer
*	@return		0
*	@note		None
*	@attention	None
*/
static void __devexit fmb_hw_remove(struct pci_dev* pci_p)
{
	int 			minor;
	struct fmb_hard_private* priv_p;

	priv_p = (struct fmb_hard_private*)pci_get_drvdata(pci_p);
	
	minor = priv_p->minor;

	MSG(DRIVER_FUNC_LVL, minor, "START");

	free_irq(priv_p->pci_dev_p->irq, priv_p);			

	Fmb_hw_reg_write_dma(priv_p, INTENABLE, 0x00000000);

	Fmb_core_remove(priv_p->core_priv_p);	

	fmb_card_powerdown(priv_p);			

	Fmb_hw_clear_irq(priv_p);			
	fmb_hw_unmemmap(priv_p);			

	pci_disable_device(pci_p);			
	
	cdev_del(&priv_p->cdev_info);				

	fmb_hw_private_data_release(priv_p);	

	s_Fmb_cards_active--;                  
	
	MSG(DRIVER_FUNC_LVL, minor, "END");
}	

/*----------------------------------------------------------------------------*/
/* Registration processing to PCI bus driver  */
/*----------------------------------------------------------------------------*/
static struct pci_device_id s_Fmb_hw_pci_tbl[] __devinitdata = {
        { FMB_PCI_VENDOR_ID, FMB_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
        { 0 }
};
MODULE_DEVICE_TABLE(pci, s_Fmb_hw_pci_tbl);

static struct pci_driver s_Fmb_hw_driver = {
	.name		=	FMB_DRIVER_NAME,
	.id_table	=	s_Fmb_hw_pci_tbl,
	.probe		=	fmb_hw_probe,
	.remove		=	fmb_hw_remove,
};

/**
*	@brief		FMB Hardware initialize module
*	@param[in]	None
*	@return		0			Normal end
*	@return		-EBUSY		Can not module registe
							Can not interrupt reuest
*	@note		None
*	@attention	None
*/  

static int __init fmb_hw_init_module(void)
{
	int 		minor;
	int 		cnt;
	int 		result;
	int			rc;

	minor = -1;
	sema_init(&sm, 1);
	spin_lock_init(&s_Fmb_hw_lock);
	MSG(DRIVER_FUNC_LVL, minor, "START");

	memset( s_Fmb_hard_private_list, 0x00, sizeof( s_Fmb_hard_private_list ) );
	for (cnt = 0; cnt < FMB_MAX_CARDS; cnt++){
		s_Fmb_hard_private_list[cnt].minor     = -1;
	}
	
	Fmb_core_init_module();

	result = alloc_chrdev_region(&s_dev, FMB_MINOR_NUM_START, FMB_MAX_CARDS, FMB_DRIVER_NAME);	
	if(result < 0){
		MSG(KERN_ERR_LVL, minor, "Majors number allocation error");
		return -EBUSY;
	}
	s_Fmb_driver_version_major = MAJOR(s_dev);
	MSG(DEBUG_LVL, minor, "Majors number = %d", s_Fmb_driver_version_major);
	
	rc = pci_register_driver (&s_Fmb_hw_driver);		
	if(rc < 0){
		MSG(KERN_ERR_LVL, minor, "PCI driver registration error");
		unregister_chrdev_region(s_dev, FMB_MAX_CARDS);		
		return -EBUSY;		
	}
	MSG(DRIVER_FUNC_LVL, minor, "END");
	return rc;
}

/**
*	@brief		FMB Hardware cleanup module
*	@param[in]	None
*	@return		None
*	@note		None
*	@attention	None
*/  

static void __exit fmb_hw_cleanup_module(void)
{
	int 		minor;
	
	minor = -1;

	MSG(DRIVER_FUNC_LVL, minor, "START");
	
	unregister_chrdev_region(s_dev, FMB_MAX_CARDS);	
	
	pci_unregister_driver (&s_Fmb_hw_driver);	

	MSG(DRIVER_FUNC_LVL, minor, "END");
}

module_init(fmb_hw_init_module);
module_exit(fmb_hw_cleanup_module);