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authorRichard Henderson <richard.henderson@linaro.org>2024-05-29 10:36:25 -0700
committerPeter Maydell <peter.maydell@linaro.org>2024-05-30 14:31:38 +0100
commitf2dce4dc10df4e23e0b4300c5a43a2c05aa85013 (patch)
tree2ec2c48af9c8b4467c43cee1b372e2564e0b878c
parent8d87f1c1cd58eb41d8ffb9399a0c6ec6b35929b7 (diff)
risugen/arm: Refine prefetch and memory hintspace patternsHEADmaster
Avoid prefetch patterns that are UNPREDICTABLE. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240529173625.800102-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--thumb.risu15
1 files changed, 14 insertions, 1 deletions
diff --git a/thumb.risu b/thumb.risu
index 357b791..6a05bf2 100644
--- a/thumb.risu
+++ b/thumb.risu
@@ -33,7 +33,20 @@ SMMUL T1 11111 0110 101 rn:4 1111 rd:4 000 r rm:4
# preload and memory hint space (in the byte and halfword
# load space, where Rt == 15).
# The constraint is to avoid UNPREDICTABLE space
-HINTSPACE T1 111 1100 op1:2 0 z 1 y:4 1111 op2:6 any:6 { ($y == 15) || (($op1 & 1) != 0) || !((($op2 & 0x24) == 0x24) || (($op2 & 0x3c) == 0x38)) ; }
+PLD_pi TI 1111 1000 10 w 1 rn:4 1111 imm:12 { $rn != 0xf; }
+PLD_ni TI 1111 1000 00 w 1 rn:4 1111 1100 imm:8 { $rn != 0xf; }
+PLD_li TI 1111 1000 u 00 1 1111 1111 imm:12
+PLD_rr TI 1111 1000 00 w 1 rn:4 1111 000000 imm:2 rm:4 \
+ { $rn != 0xf && $rm != 0xf; }
+PLI_pi TI 1111 1001 1 00 1 rn:4 1111 imm:12 { $rn != 0xf; }
+PLI_ni TI 1111 1001 0 00 1 rn:4 1111 1100 imm:8 { $rn != 0xf; }
+PLI_li TI 1111 1001 u 00 1 1111 1111 imm:12
+PLI_rr TI 1111 1001 0 00 1 rn:4 1111 000000 imm:2 rm:4 \
+ { $rn != 0xf && $rm != 0xf; }
+HINTSPACE_rr T1 1111 1001 0011 rn:4 1111 000000 imm:2 rm:4 { $rn != 0xf; }
+HINTSPACE_ni T1 1111 1001 0011 rn:4 1111 1100 imm:8 { $rn != 0xf; }
+HINTSPACE_pi T1 1111 1001 1011 rn:4 1111 imm:12 { $rn != 0xf; }
+HINTSPACE_li T1 1111 1001 u 011 1111 1111 imm:12
# VMLAL, VMLSL, VQDMLAL, VQDMLSL, VMULL, VQDMULL
# NB that enc T1 is actually VMLA/VMLS only, T2 is VMLAL/VMLSL only