diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-25 15:58:13 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-06-03 16:43:26 +0100 |
| commit | 81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1 (patch) | |
| tree | e5e56230ae43c544d8d05ba36c910289ff9d1c40 /target/arm/sve.decode | |
| parent | 839144784b613998edf7a7277ed2ed2015b0b4d7 (diff) | |
target/arm: Implement bfloat16 matrix multiply accumulate
This is BFMMLA for both AArch64 AdvSIMD and SVE,
and VMMLA.BF16 for AArch32 NEON.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525225817.400336-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 51f87e8937..6c17898dee 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1568,8 +1568,10 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm ### SVE2 floating point matrix multiply accumulate - -FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm +{ + BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 + FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm +} ### SVE2 Memory Gather Load Group |