From 81266a1f58bf557280c6f7ce3cad1ba8ed8a56f1 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 25 May 2021 15:58:13 -0700 Subject: target/arm: Implement bfloat16 matrix multiply accumulate This is BFMMLA for both AArch64 AdvSIMD and SVE, and VMMLA.BF16 for AArch32 NEON. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210525225817.400336-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve.decode | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'target/arm/sve.decode') diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 51f87e8937..6c17898dee 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1568,8 +1568,10 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm ### SVE2 floating point matrix multiply accumulate - -FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm +{ + BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 + FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm +} ### SVE2 Memory Gather Load Group -- cgit v1.2.3