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-rw-r--r--tcl/target/stm32l.cfg4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg
index eea082e6..8e6a10e1 100644
--- a/tcl/target/stm32l.cfg
+++ b/tcl/target/stm32l.cfg
@@ -48,7 +48,7 @@ if { [info exists BSTAPID] } {
jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
@@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
proc stm32l_enable_HSI {} {
# Enable HSI as clock source