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authorMaciej W. Rozycki <macro@imgtec.com>2017-06-28 02:07:36 +0100
committerMaciej W. Rozycki <macro@imgtec.com>2017-06-28 02:07:36 +0100
commit819e1f86976dbbd13e0de004cdd3e3089e4c3fc0 (patch)
tree7f1099af6db6bbbd9a4ce344712d19b116006547 /ld
parentc7d289d129cde92c0d351446c5072c5f744040fe (diff)
MIPS: Add new Imagination interAptiv MR2 GAS and LD tests
Add GAS tests to verify Imagination interAptiv MR2 instruction assembly, disassembly and ELF object file flags. Add LD tests to verify Imagination interAptiv MR2 ELF object file link-time compatibility and flag merging/propagation. Use the framework enhancement added with commit 7575e6a752ec ("MIPS/LD/testsuite: mips-elf-flags: Add MIPS ABI Flags handling"). gas/ * testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test. * testsuite/gas/mips/save-err.d: New test. * testsuite/gas/mips/save-sub.d: New test. * testsuite/gas/mips/interaptiv-mr2@save.d: New test. * testsuite/gas/mips/mips1@save-sub.d: New test. * testsuite/gas/mips/mips2@save-sub.d: New test. * testsuite/gas/mips/mips3@save-sub.d: New test. * testsuite/gas/mips/mips4@save-sub.d: New test. * testsuite/gas/mips/mips5@save-sub.d: New test. * testsuite/gas/mips/mips32@save-sub.d: New test. * testsuite/gas/mips/mips64@save-sub.d: New test. * testsuite/gas/mips/mips16@save-sub.d: New test. * testsuite/gas/mips/mips16e@save-sub.d: New test. * testsuite/gas/mips/r3000@save-sub.d: New test. * testsuite/gas/mips/r3900@save-sub.d: New test. * testsuite/gas/mips/r4000@save-sub.d: New test. * testsuite/gas/mips/vr5400@save-sub.d: New test. * testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test. * testsuite/gas/mips/sb1@save-sub.d: New test. * testsuite/gas/mips/octeon2@save-sub.d: New test. * testsuite/gas/mips/octeon3@save-sub.d: New test. * testsuite/gas/mips/xlr@save-sub.d: New test. * testsuite/gas/mips/r5900@save-sub.d: New test. * testsuite/gas/mips/mips16e2-copy.d: New test. * testsuite/gas/mips/mips16e2-copy-err.d: New test. * testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name' option. Adjust for trailing padding change. * testsuite/gas/mips/mips16e2-copy-err.l: New stderr output. * testsuite/gas/mips/save-sub.s: New test source. * testsuite/gas/mips/mips16e2-copy.s: New test source. * testsuite/gas/mips/mips16e2-copy-err.s: New test source. * testsuite/gas/mips/save.s: Update description, change trailing padding and remove trailing white space. * testsuite/gas/mips/mips.exp: Expand `save' and `save-err' tests across the regular MIPS interAptiv MR2 architecture. Run the new tests. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2 tests.
Diffstat (limited to 'ld')
-rw-r--r--ld/ChangeLog5
-rw-r--r--ld/testsuite/ld-mips-elf/mips-elf-flags.exp45
2 files changed, 50 insertions, 0 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog
index fec44c9b02..8c80daf2f3 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2
+ tests.
+
2017-06-27 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
PR ld/13402
diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
index dbe4132c56..71ed5d63a7 100644
--- a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
+++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
@@ -199,6 +199,17 @@ isa_conflict { "-march=r5900 -32" "-march=vr4111 -32" } 5900 4111
isa_conflict { "-march=loongson2e -32" "-march=loongson2f -32" } loongson_2e loongson_2f
isa_conflict { "-march=loongson3a -32" "-march=loongson2f -32" } loongson_3a loongson_2f
+isa_conflict { "-march=interaptiv-mr2 -32" \
+ "-march=r4010 -32" } interaptiv-mr2 4010
+isa_conflict { "-march=interaptiv-mr2 -mnan=2008 -mfp64 -32" \
+ "-mips32r6 -32" } interaptiv-mr2 isa32r6
+isa_conflict { "-march=interaptiv-mr2 -32" \
+ "-mips3 -32" } interaptiv-mr2 4000
+isa_conflict { "-march=interaptiv-mr2 -32" \
+ "-mips64r2 -32" } interaptiv-mr2 isa64r2
+isa_conflict { "-march=interaptiv-mr2 -32" \
+ "-march=octeon -32" } interaptiv-mr2 octeon
+
regsize_conflict { "-mips4 -mgp64 -mabi=o64" "-mips2 -32" }
regsize_conflict { "-mips4 -mabi=o64" "-mips4 -mabi=32" }
regsize_conflict { "-mips4 -mabi=eabi -mgp32" "-mips4 -mabi=eabi -mgp64" }
@@ -225,3 +236,37 @@ good_combination { "-march=sb1 -mgp32 -32" "-march=4000 -mgp32 -32" } { sb1 o3
good_combination { "-mips32 -mabi=32" "-march=sb1 -mabi=32" } { sb1 o32 }
good_combination { "-mips64r2 -mabi=32" "-mips32 -mabi=32" } { mips64r2 o32 }
good_combination { "-mips5 -mabi=o64" "-mips64r2 -mabi=o64" } { mips64r2 o64 }
+
+good_combination { "-march=interaptiv-mr2 -32" "-mips1 -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r3 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
+good_combination { "-march=interaptiv-mr2 -32" "-mips32r2 -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r3 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
+good_combination { "-march=interaptiv-mr2 -32" "-march=interaptiv -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r3 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
+good_combination { "-march=interaptiv-mr2 -32" "-mips32r3 -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r3 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
+good_combination { "-march=interaptiv-mr2 -32" "-mips32r3 -mips16 -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r3 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" "MIPS16 ASE" }
+good_combination { "-march=interaptiv-mr2 -mips16 -32" "-mips32r3 -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r3 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" \
+ "MIPS16 ASE" "MIPS16e2 ASE" }
+good_combination { "-march=interaptiv-mr2 -32" "-mips32r5 -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r5 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
+good_combination { "-march=interaptiv-mr2 -32" "-march=m5100 -32" } \
+ { mips32r2 interaptiv-mr2 } \
+ MIPS32r5 "Imagination interAptiv MR2" \
+ { "DSP ASE" "Enhanced VA Scheme" "MT ASE" }