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| author | Kito Cheng <kito.cheng@gmail.com> | 2017-03-07 18:15:02 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-15 07:47:52 -0700 |
| commit | b416fe873ef44b2a613c9266c6462a481926d986 (patch) | |
| tree | 508c7f088305d110f17dd84951738a17314a7722 /gold | |
| parent | 03b039a518fa0f89a9900a44a8b874cc91061305 (diff) | |
RISC-V: Fix assembler for c.li, c.andi and c.addiw
- They can accept 0 in imm field
2017-03-14 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
<c.andi>: Likewise.
<c.addiw> Likewise.
Diffstat (limited to 'gold')
0 files changed, 0 insertions, 0 deletions