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authorLinus Torvalds <torvalds@linux-foundation.org>2020-04-02 15:54:13 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2020-04-02 15:54:13 -0700
commit5c8db3eb381745c010ba746373a279e92502bdc8 (patch)
tree69c1d8b8180635c6230fce57830e38e3f8d26cef /drivers/i2c/busses/i2c-exynos5.c
parent848960e576dafc8ed54c691b2f70b92e1fdea9ba (diff)
parentdf576beee53ac97fe0a413430e623e658805891d (diff)
Merge branch 'i2c/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang: "I2C has: - using defines for bus speeds to avoid mistakes in hardcoded values; lots of small driver updates because of that. Thanks, Andy! - API change: i2c_setup_smbus_alert() was renamed to i2c_new_smbus_alert_device() and returns ERRPTR now. All in-tree users have been converted - in the core, a rare race condition when deleting the cdev has been fixed. Thanks, Kevin! - lots of driver updates. Thanks, everyone! I also want to mention: The amount of review and testing tags given was quite high this time. Thank you to these people, too. I hope we can keep it like this!" * 'i2c/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (34 commits) i2c: rcar: clean up after refactoring i2c_timings macintosh: convert to i2c_new_scanned_device i2c: drivers: Use generic definitions for bus frequencies i2c: algo: Use generic definitions for bus frequencies i2c: stm32f7: switch to I²C generic property parsing i2c: rcar: Consolidate timings calls in rcar_i2c_clock_calculate() i2c: core: Allow override timing properties with 0 i2c: core: Provide generic definitions for bus frequencies i2c: mxs: Use dma_request_chan() instead dma_request_slave_channel() i2c: imx: remove duplicate print after platform_get_irq() i2c: designware: Fix spelling typos in the comments i2c: designware: Discard i2c_dw_read_comp_param() function i2c: designware: Detect the FIFO size in the common code i2c: dev: Fix the race between the release of i2c_dev and cdev i2c: qcom-geni: Drop of_platform.h include i2c: qcom-geni: Grow a dev pointer to simplify code i2c: qcom-geni: Let firmware specify irq trigger flags i2c: stm32f7: do not backup read-only PECR register i2c: smbus: remove outdated references to irq level triggers i2c: convert SMBus alert setup function to return an ERRPTR ...
Diffstat (limited to 'drivers/i2c/busses/i2c-exynos5.c')
-rw-r--r--drivers/i2c/busses/i2c-exynos5.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index e7514c16b756c..527030953ba13 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -164,13 +164,6 @@
#define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
#define MASTER_ID(x) ((x & 0x7) + 0x08)
-/*
- * Controller operating frequency, timing values for operation
- * are calculated against this frequency
- */
-#define HSI2C_HS_TX_CLOCK 1000000
-#define HSI2C_FS_TX_CLOCK 100000
-
#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
enum i2c_type_exynos {
@@ -264,6 +257,9 @@ static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
* exynos5_i2c_set_timing: updates the registers with appropriate
* timing values calculated
*
+ * Timing values for operation are calculated against either 100kHz
+ * or 1MHz controller operating frequency.
+ *
* Returns 0 on success, -EINVAL if the cycle length cannot
* be calculated.
*/
@@ -281,7 +277,7 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
unsigned int t_ftl_cycle;
unsigned int clkin = clk_get_rate(i2c->clk);
unsigned int op_clk = hs_timings ? i2c->op_clock :
- (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK :
+ (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
i2c->op_clock;
int div, clk_cycle, temp;
@@ -353,7 +349,7 @@ static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
/* always set Fast Speed timings */
int ret = exynos5_i2c_set_timing(i2c, false);
- if (ret < 0 || i2c->op_clock < HSI2C_HS_TX_CLOCK)
+ if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
return ret;
return exynos5_i2c_set_timing(i2c, true);
@@ -376,7 +372,7 @@ static void exynos5_i2c_init(struct exynos5_i2c *i2c)
i2c->regs + HSI2C_CTL);
writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
- if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
+ if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
i2c->regs + HSI2C_ADDR);
i2c_conf |= HSI2C_HS_MODE;
@@ -748,7 +744,7 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
return -ENOMEM;
if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
- i2c->op_clock = HSI2C_FS_TX_CLOCK;
+ i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
i2c->adap.owner = THIS_MODULE;