checkpoint

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/constant@265567 138bc75d-0d04-0410-961f-82ee72b054a4

2 files changed, 51 insertions, 45 deletions

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c6b9cdc1d54..1001013168d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,18 @@
 2018-10-28  Michael Meissner  <meissner@linux.ibm.com>
 
+	* config/rs6000/rs6000.md (UNSPEC_SF_CONSTANT): Split into 2
+	separate unspecs.
+	(UNSPEC_SF_CONSTANT_VSX): Likewise.
+	(UNSPEC_SF_CONSTANT_MEM): Likewise.
+	(movsf_const_direct_move): Go back to just handling VSX
+	registers.  Change UNSPEC.
+	(movsf_const_internal1): Likewise.
+	(movsf_const_memory): Rework optimizing storing constant to
+	memory.
+	(movsf_const_internal2): Likewise.
+
+2018-10-28  Michael Meissner  <meissner@linux.ibm.com>
+
 	* config/rs6000/rs6000.md (movsf_const_direct_move): Rework move
 	to GPR and memory.
 	(movsf_const_internal1): Likewise.
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a70c674ea5f..742bf5d8caa 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -147,7 +147,8 @@
    UNSPEC_SIGNBIT
    UNSPEC_SF_FROM_SI
    UNSPEC_SI_FROM_SF
-   UNSPEC_SF_CONSTANT
+   UNSPEC_SF_CONSTANT_VSX
+   UNSPEC_SF_CONSTANT_MEM
   ])
 
 ;;
@@ -7285,40 +7286,26 @@
 ;; SFmode since we are moving it to a VSX register.  The power8's direct move
 ;; is too slow, so only do this on power9 systems and later.
 (define_insn_and_split "movsf_const_direct_move"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=wa,b,m")
-	(match_operand:SF 1 "easy_fp_direct_move_constant" "wG,wG,wG"))
-   (clobber (match_scratch:DI 2 "=b,b,b"))]
+  [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
+	(match_operand:SF 1 "easy_fp_direct_move_constant" "wG"))
+   (clobber (match_scratch:DI 2 "=b"))]
   "TARGET_P9_VECTOR && TARGET_POWERPC64"
   "#"
   "&& reload_completed"
   [(set (match_dup 2)
 	(match_dup 3))
    (set (match_dup 0)
-	(unspec:SF [(match_dup 2)
-		    (match_dup 4)] UNSPEC_SF_CONSTANT))]
+	(unspec:SF [(match_dup 2)] UNSPEC_SF_CONSTANT_VSX))]
 {
   rtx src = operands[1];
-  /* VSX register.  */
-  if (which_alternative == 0)
-    {
-      int endian = (WORDS_BIG_ENDIAN == 0);
-      long l[2];
-      HOST_WIDE_INT val;
-      REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (src), l);
-      val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
-	     | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
+  int endian = (WORDS_BIG_ENDIAN == 0);
+  long l[2];
+  HOST_WIDE_INT val;
+  REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (src), l);
+  val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
+	 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
 
-      operands[3] = GEN_INT (val);
-      operands[4] = const0_rtx;
-    }
-  /* GPR register or memory.  */
-  else
-    {
-      long l;
-      REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (src), l);
-      operands[3] = GEN_INT (l);
-      operands[4] = const1_rtx;
-    }
+  operands[3] = GEN_INT (val);
 })
 
 ;; Move SF constant to a VSX register.  We need to prevent the normal direct
@@ -7326,31 +7313,37 @@
 ;; to DFmode, since we have loaded up the constant in the final DFmode format.
 (define_insn "*movsf_const_internal1"
   [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
-	(unspec:SF [(match_operand:DI 1 "int_reg_operand" "r")
-		    (const_int 0)]
-		   UNSPEC_SF_CONSTANT))]
+	(unspec:SF [(match_operand:DI 1 "int_reg_operand" "r")]
+		   UNSPEC_SF_CONSTANT_VSX))]
   "TARGET_P9_VECTOR && TARGET_POWERPC64"
   "mtvsrd %x0,%1"
   [(set_attr "type" "mffgpr")])
 
-;; Optimize storing SFmode constants to memory or a GPR.
-(define_insn_and_split "*movsf_const_internal2"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=m,r,r")
-	(unspec:SF [(match_operand:DI 1 "int_reg_operand" "r,0,r")
-		    (const_int 1)]
-		   UNSPEC_SF_CONSTANT))]
+;; Optimize storing SFmode constants to memory.
+(define_insn_and_split "movsf_const_memory"
+  [(set (match_operand:SF 0 "memory_operand" "=m")
+	(match_operand:SF 1 "easy_fp_direct_move_constant" "wG"))
+   (clobber (match_scratch:DI 2 "=b"))]
   "TARGET_P9_VECTOR && TARGET_POWERPC64"
-  "@
-   stw%U0%X0 %1,%0
-   #
-   mr %0,%1"
-  "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
-  [(const_int 0)]
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 2)
+	(match_dup 3))
+   (set (match_dup 0)
+	(unspec:SF [(match_dup 2)] UNSPEC_SF_CONSTANT_MEM))]
 {
-  emit_note (NOTE_INSN_DELETED);
-  DONE;
-}
-  [(set_attr "type" "store,*,*")])
+  long l;
+  REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
+  operands[3] = GEN_INT (l);
+})
+
+(define_insn "*movsf_const_memory2"
+  [(set (match_operand:SF 0 "memory_operand" "=m")
+	(unspec:SF [(match_operand:DI 1 "int_reg_operand" "r")]
+		   UNSPEC_SF_CONSTANT_MEM))]
+  "TARGET_P9_VECTOR && TARGET_POWERPC64"
+  "stw%U0%X0 %1,%0"
+  [(set_attr "type" "store")])
 
 ;;	LWZ          LFIWZX     STW        STFIWX     MTVSRWZ    MFVSRWZ
 ;;	FMR          MR         MT%0       MF%1       NOP