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authormeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>2019-10-16 06:01:24 +0000
committermeissner <meissner@138bc75d-0d04-0410-961f-82ee72b054a4>2019-10-16 06:01:24 +0000
commit4a71634e97b1fdfe2455d8220bef98a62b061593 (patch)
tree5db13d6c45a46f6f22e771f81ef0add4efeaad6e
parent3aa6a5043ae404cff7c37608cd69848348dbbe86 (diff)
Undo part of patch #4
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/ibm/pcrel-trunk@277052 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/config/rs6000/rs6000.md78
1 files changed, 6 insertions, 72 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d6b7c6d2360..f651798ff39 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11559,43 +11559,14 @@
[(set_attr "type" "three")
(set_attr "length" "12")])
-;; We can't use the prefixed attribute here because there are two memory
-;; instructions. We can't split the insn due to the fact that this operation
-;; needs to be done in one piece.
(define_insn "stack_protect_setdi"
[(set (match_operand:DI 0 "memory_operand" "=Y")
(unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
(set (match_scratch:DI 2 "=&r") (const_int 0))]
"TARGET_64BIT"
-{
- if (prefixed_memory (operands[1], DImode))
- output_asm_insn ("pld %2,%1", operands);
- else
- output_asm_insn ("ld%U1%X1 %2,%1", operands);
-
- if (prefixed_memory (operands[0], DImode))
- output_asm_insn ("pstd %2,%0", operands);
- else
- output_asm_insn ("std%U0%X0 %2,%0", operands);
-
- return "li %2,0";
-}
+ "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
[(set_attr "type" "three")
-
- ;; Back to back prefixed memory instructions take 20 bytes (8 bytes for each
- ;; prefixed instruction + 4 bytes for the possible NOP). Add in 4 bytes for
- ;; the LI 0 at the end.
- (set_attr "prefixed" "no")
- (set (attr "length")
- (cond [(and (match_operand 0 "prefixed_memory")
- (match_operand 1 "prefixed_memory"))
- (const_string "24")
-
- (ior (match_operand 0 "prefixed_memory")
- (match_operand 1 "prefixed_memory"))
- (const_string "20")]
-
- (const_string "12")))])
+ (set_attr "length" "12")])
(define_expand "stack_protect_test"
[(match_operand 0 "memory_operand")
@@ -11634,9 +11605,6 @@
lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
[(set_attr "length" "16,20")])
-;; We can't use the prefixed attribute here because there are two memory
-;; instructions. We can't split the insn due to the fact that this operation
-;; needs to be done in one piece.
(define_insn "stack_protect_testdi"
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
(unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
@@ -11645,44 +11613,10 @@
(set (match_scratch:DI 4 "=r,r") (const_int 0))
(clobber (match_scratch:DI 3 "=&r,&r"))]
"TARGET_64BIT"
-{
- if (prefixed_memory (operands[1], DImode))
- output_asm_insn ("pld %3,%1", operands);
- else
- output_asm_insn ("ld%U1%X1 %3,%1", operands);
-
- if (prefixed_memory (operands[2], DImode))
- output_asm_insn ("pld %4,%2", operands);
- else
- output_asm_insn ("ld%U2%X2 %4,%2", operands);
-
- if (which_alternative == 0)
- output_asm_insn ("xor. %3,%3,%4", operands);
- else
- output_asm_insn ("cmpld %0,%3,%4\;li %3,0", operands);
-
- return "li %4,0";
-}
- ;; Back to back prefixed memory instructions take 20 bytes (8 bytes for each
- ;; prefixed instruction + 4 bytes for the possible NOP). Add in either 4 or
- ;; 8 bytes to do the test.
- [(set_attr "prefixed" "no")
- (set (attr "length")
- (cond [(and (match_operand 1 "prefixed_memory")
- (match_operand 2 "prefixed_memory"))
- (if_then_else (eq_attr "alternative" "0")
- (const_string "28")
- (const_string "32"))
-
- (ior (match_operand 1 "prefixed_memory")
- (match_operand 2 "prefixed_memory"))
- (if_then_else (eq_attr "alternative" "0")
- (const_string "20")
- (const_string "24"))]
-
- (if_then_else (eq_attr "alternative" "0")
- (const_string "16")
- (const_string "20"))))])
+ "@
+ ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
+ ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
+ [(set_attr "length" "16,20")])
;; Here are the actual compare insns.