diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-09-26 19:04:23 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2018-09-27 13:15:19 +0530 |
| commit | 5e49674755ce8d56d17dbc1d0f3b68bbf8b3dd70 (patch) | |
| tree | 9b1eb573128ab6aaf5df4f893db6c9867305d5d0 | |
This commit imports and transpositions the original 96Boards CE
Spec v1.0 release.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
| -rw-r--r-- | LICENSE | 428 | ||||
| -rw-r--r-- | Makefile | 20 | ||||
| -rw-r--r-- | README.rst | 118 | ||||
| -rw-r--r-- | source/chapter1-background.rst | 55 | ||||
| -rw-r--r-- | source/chapter2-96b-ce.rst | 640 | ||||
| -rw-r--r-- | source/chapter3-references.rst | 17 | ||||
| -rw-r--r-- | source/chapter4-appendix.rst | 506 | ||||
| -rw-r--r-- | source/conf.py | 164 | ||||
| -rw-r--r-- | source/images/96b_ce_ext_2x.png | bin | 0 -> 71531 bytes | |||
| -rw-r--r-- | source/images/96b_ce_std_2x.png | bin | 0 -> 61602 bytes | |||
| -rw-r--r-- | source/images/cc-by-sa-4.0-88x31.eps | 2727 | ||||
| -rw-r--r-- | source/images/cc-by-sa-4.0-88x31.png | bin | 0 -> 1697 bytes | |||
| -rw-r--r-- | source/images/usb.png | bin | 0 -> 55706 bytes | |||
| -rw-r--r-- | source/index.rst | 37 |
14 files changed, 4712 insertions, 0 deletions
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For +the avoidance of doubt, this paragraph does not form part of the +public licenses. + +Creative Commons may be contacted at creativecommons.org. + diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..d161ef7 --- /dev/null +++ b/Makefile @@ -0,0 +1,20 @@ +# Minimal makefile for Sphinx documentation +# + +# You can set these variables from the command line. +SPHINXOPTS = +SPHINXBUILD = sphinx-build +SPHINXPROJ = 96Boards-CE-Spec +SOURCEDIR = source +BUILDDIR = build + +# Put it first so that "make" without argument is like "make help". +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) + +.PHONY: help Makefile + +# Catch-all target: route all unknown targets to Sphinx using the new +# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). +%: Makefile + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) diff --git a/README.rst b/README.rst new file mode 100644 index 0000000..66e0c78 --- /dev/null +++ b/README.rst @@ -0,0 +1,118 @@ +######################################## +96Boards Consumer Edition Specification +######################################## + +96Boards Consumer Edition Specification. + +Build Instructions +================== + +Requirements +^^^^^^^^^^^^ + +* Sphinx version 1.5 or later: http://sphinx-doc.org/contents.html +* LaTeX (and pdflatex, and various LaTeX packages) + +On Debian and Ubuntu +^^^^^^^^^^^^^^^^^^^^ +:: + + # apt-get install python-sphinx texlive texlive-latex-extra libalgorithm-diff-perl \ + texlive-humanities texlive-generic-recommended texlive-generic-extra \ + latexmk + +If the version of python-sphinx installed is too old, then an additional +new version can be installed with the Python package installer:: + + $ apt-get install python-pip + $ pip install --user --upgrade Sphinx + $ export SPHINXBUILD=~/.local/bin/sphinx-build + +Export SPHINXBUILD (see above) if Sphinx was installed with pip --user, then follow Make commands below + +On Fedora +^^^^^^^^^ + +:: + + # dnf install python2-sphinx texlive texlive-capt-of texlive-draftwatermark \ + texlive-fncychap texlive-framed texlive-needspace \ + texlive-tabulary texlive-titlesec texlive-upquote \ + texlive-wrapfig + +It is also possible to use python3-sphinx; this requires +SPHINXBUILD=sphinx-build-3 to be passed on the Make command line. + +On Mac OS X +^^^^^^^^^^^ + +* Install MacTeX_ +* Install pip if you do not have it:: + + $ sudo easy_install pip + +* Install Sphinx:: + + $ pip install --user --upgrade Sphinx + +.. _MacTeX: http://tug.org/mactex + +Make Targets +^^^^^^^^^^^^ + +To generate PDF:: + + $ make latexpdf + +To generate hierarchy of HTML pages:: + + $ make html + +To generate a single HTML page:: + + $ make singlehtml + +Output goes in `./build` subdirectory. + +License +======= + +This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 +International License (CC-BY-SA-4.0). To view a copy of this license, visit +http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to +Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. + +Contributions are accepted under the same with sign-off under the Developer's +Certificate of Origin. For more on contributing to {PROJECT}, see CONTRIBUTING.rst_. + +A copy of the license is included in the LICENSE_ file. + +.. image:: https://i.creativecommons.org/l/by-sa/4.0/88x31.png + :target: http://creativecommons.org/licenses/by-sa/4.0/ + :alt: Creative Commons License + +.. _CONTRIBUTING.rst: ./CONTRIBUTING.rst +.. _LICENSE: ./LICENSE + +Writers Guide +============= + +All documentation in this repository uses reStructuredText_ markup +with Sphinx_ extensions. + +All files in this project must include the relevant SPDX license identifier +tag. Generally this means each ``.rst`` file should include the line + + ``.. SPDX-License-Identifier: CC-BY-SA-4.0`` + +.. _reStructuredText: http://docutils.sourceforge.net/docs/user/rst/quickref.html +.. _Sphinx: http://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html + +Original Document +================= +Prior to being relicensed to CC-BY-SA 4.0, this specification was +released by Linaro. The original Draft v1.0 text can be found here: + +`{PROJECT} Draft v1.0 <https://linaro.co/ce-specification>`_ + +.. SPDX-License-Identifier: CC-BY-SA-4.0 diff --git a/source/chapter1-background.rst b/source/chapter1-background.rst new file mode 100644 index 0000000..c402cd3 --- /dev/null +++ b/source/chapter1-background.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +********** +Background +********** + +The 96Boards Consumer Edition (CE) Platform is intended to support: + +1. Low cost Single Board Computer use + + a) Low cost platform for running standard Linux-based OS including Android + b) Open Source community software development + +2) Maker community + + a) Requiring extensible hardware interfaces to prototype or build add on + products + +3) Embedded System OEMs requiring low cost off-the-shelf CPU modules + + a) Example - Kiosks, Displays, Robots etc. + +4) Community engineering activities, including + + a) upstream development + b) allowing ‘real life’ benchmarking and tuning, including power management + c) being integrated into an automated test farm + d) 96Boards Community program to be run by Linaro + +In all cases key design and distribution goals are: + +- Low cost ($50-100 retail for a minimum configuration) + +- Easy to extend with off the shelf parts available to maker community and OEMs + +- Easy to purchase globally (for example, via Amazon, Alibaba, Farnell, Digikey, + Mouser etc.) + +- Enable a third party ecosystem to develop around expansion (mezzanine) + boards/peripherals/displays etc. that can be used on any 96Boards CE compliant + board + +A key design objective is to encourage multiple SoC vendors to build boards to +this specification. This is an evolution from previous successful community +boards where the external ecosystem is tied to a particular SoC. The 96Boards +CE specification is designed to enable an ecosystem to evolve that will support +multiple SoCs over a period of years. + +The specification is completely open - that is anyone may build a board to the +specification without payment of any fees or any licensing requirements. + +The 96Boards CE Certification Program is optional for board developers and will +provide hardware and software certification, a community site and software +support provided by Linaro for 96Boards CE certified boards. Participation is +not required in order to build a board to the specification. diff --git a/source/chapter2-96b-ce.rst b/source/chapter2-96b-ce.rst new file mode 100644 index 0000000..c3c9ca9 --- /dev/null +++ b/source/chapter2-96b-ce.rst @@ -0,0 +1,640 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +************************* +96Boards Consumer Edition +************************* + +Hardware +======== + +96Boards CE Minimum Hardware Features +------------------------------------- + +1) Ultra-small low-profile “card” form factor - 85 x 54 x 12mm + + a) Footprint compatible Extended Version option - 85 x 100 x 12mm + +2) Design is SoC independent (targets 32 or 64 bit SoCs) + +3) 0.5GB RAM (Minimum 1GB recommended for Android) + +4) MicroSDHC Socket for up to 64GB on-board or expansion flash storage + +5) Wifi 802.11g/n and Bluetooth 4.0 LE + +6) On Board Connectors and expansion I/O + + a) 2x USB Type A or Type C host ports (USB2.x or 3.x) + + b) USB Micro-B USB or Type C slave or OTG port (USB2.x or 3.x) + + a) For PC connection + + c) Display output must be available on one of the following: + + a) HDMI/audio on HDMI full size or micro connector + + b) MHL display/audio on display microUSB + + c) DisplayPort/audio on USB Type C + + d) Low profile 40 way female header for maker/community use + + d) Low profile 60 way high speed female module header for advanced + maker/OEM use with high speed interfaces including MIPI-DSI, USB and + optional MIPI CSI-2 + + e) Board power from low profile DC Jack connector + +A 96Boards CE board must implement the minimum functionality. Additional functionality +may be implemented provided that the 96Boards CE specifications are implemented in full +(including limitations on form factor). See below for further information. + +Hardware Feature Details +------------------------ + +96Boards CE Physical Footprint +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The 96Boards CE defines a new standard for small footprint community boards. The board is +defined into a credit card footprint with a total maximum height of 12.0mm: + +1) Area + + The board without population of connectors shall fit into a 85 x 54mm + footprint +/-0.25mm. Connectors should not protrude from the area + footprint except as component design requires (for example USB Type A + front shrouds). A compatible extended version is defined that shall fit + into a 85 x 100mm footprint with the same conditions. + +2) Height + + a) PCB 62mil 62mil (1.575mm) nominal + b) Below PCB 3.4 mm maximum + c) Above PCB 7.0 mm maximum + +Total height of the board including on board connectors **shall** not +exceed 12mm. + +Note that the maximum height for general components on the board top side is +4mm (not including the allowed areas for connectors and larger components). +The maximum height in the allowed areas is 6.5mm except for the two Type A +USB connectors which can be up to 7.0mm. The extended version does allow some +components to exceed the height specifications. See the keepout drawings in the +Specification Appendix for further information. + +SoC Location Options +^^^^^^^^^^^^^^^^^^^^ + +The specification is designed with two possible locations for the SoC. One is +on the board top surface, and the other is on the board bottom surface. + +The rationale is to permit SoCs with low power dissipation to be placed on the +top surface with a low profile heatsink or fan if required (to a total maximum +height of 6.0mm). Then, mezzanine boards placed above this area are required +to have no components on their underside corresponding keep out area above the +SoC. + +The second option is to place the SoC on the underside of the board. This +is intended for implementations that require higher SoC power dissipation. As +supplied, the board should meet the “below PCB” footprint requirement. This +then allows additional thermal management in the case or enclosure for the +board as required. + +DRAM +^^^^ + +The board **shall** be populated with a minimum of 0.5GB of DRAM. It is +**strongly recommended** that a minimum of 1GB DRAM is fitted where the +board is expected to run Android. + +eMMC/Flash +^^^^^^^^^^ + +The board **may** optionally be populated with eMMC or other format flash +memory. + +If the SoC used is not able to boot from microSDHC then a minimum +of 8MB of bootable flash memory **shall** be provided on the board. +Where multiple boot options are provided the choice of boot location **shall** +be user selectable in hardware (links or switches). + +Note that the insertion of a cable **shall not** automatically require boot +from that cable (for example the insertion of a microUSB cable into an OTG +port to use FastBoot). In this case the boot option must still be user +selectable. + +microSDHC +^^^^^^^^^ + +A microSDHC card socket **shall** be fitted in the specified location on +the board. In the absence of on-board Flash memory, the system **shall** +be capable of booting from the boot software installed on a microSDHC card +at power up. + +WiFi/Bluetooth LE +^^^^^^^^^^^^^^^^^ + +The board **shall** support WiFi (minimally 802.11g/n) and Bluetooth +4.0 (Bluetooth Low Energy). It is **recommended** that WiFi 802.11ac is +also supported. A PCB or chip antenna **shall** be provided in the prescribed +location. An external antenna socket option **may** be provided. + +Display Interface +^^^^^^^^^^^^^^^^^ + +Display output **shall** be one of: + +1) HDMI which **shall** be provided on a full size (Type A) or a micro + Type D connector + +2) MHL which **shall** be provided on a 5 pin microUSB connector + +3) Displayport which **shall** be provided on a USB Type C connector + +In all cases the display interface **shall** include audio with support for +at least 1 channel + +In all cases the connector **shall** be located in the specified location. + +A MIPI DSI port **shall** be provided on the expansion bus interface. 1-4 +lanes are supported. An implementation **may** use less than 4 lanes. + +Note that if a single DSI interface on the SoC is used to provide both + + 1) the high speed expansion bus interface DSI port + 2) the on board HDMI/MHL/DisplayPort interface (via suitable transmitter), + then the expansion port interface **shall** be operational if a + mezzanine board that uses DSI is fitted. It is then optional as to + whether the on-board interface is usable at the same time. + +Camera Interfaces +^^^^^^^^^^^^^^^^^ + +1 or 2 MIPI CSI-2 ports **may** be provided on the expansion bus interface. + +If 1 port is provided it **shall** be located on the CSI0 port interface + +From 1-4 lanes **may** be implemented on the CSI0 port interface + +From 1-2 lanes **may** be implemented on the CSI1 port interface + +An implementation **may** support dual (stereo) cameras through the +CSI0 interface if the SoC provides the necessary functionality. + +Cameras/Sensors can require additional control signals including RST, PWRDN +and MCLK. + +The specified GPIO and CLK signals on the expansion connectors +**shall** be used for these functions if implemented. + +If the cameras/sensors are not available/used then these signals **shall** +be available as GPIO and CLK signals. + +USB Ports +^^^^^^^^^ + +A total of 4 USB ports **shall** be provided for a board. + +Two Type A or Type C USB host ports (USB 2.x or 3.x) **shall** be provided +on the board. + +The connectors **shall** be in the specified locations. + +Two options are provided for the required third USB port, which **shall** +be capable of slave operation: + +1) A 5 pin microUSB USB 2.0 slave port **shall** be provided. + + The connector type **shall** be micro-AB for an OTG port or micro-B for + a slave only port. + + This port **shall not** provide power to the board, + due to insufficient power rating. + +2) A Type C USB port shall be provided (USB 2.x or 3.x). + + This port may also be used to provide 5V external power to the board. + + In both options the connector **shall** be placed in the specified location. + + The third port **shall** be available as a slave port. + + The third port **may** be an OTG port. + +A fourth USB host port **shall** be provided on the high speed expansion bus. + +Implementation note: some mobile SoCs implement only a single USB OTG port. +Such SoCs can be used on boards with a switch and a USB hub IC. See the +Appendix to this specification for an example implementation. + +Therefore, there **may** be some restrictions on simultaneous USB port usage. + +Two examples: + + a) it may not be possible to use the host ports simultaneously with the + slave port + b) a base board port may be shared via a switch to provide the expansion port + +Any such restrictions **shall** be clearly documented. + +Audio +^^^^^ + +The board **shall** provide a minimum of single channel audio through the +following facilities: + +1) I/O via Bluetooth 4.0 + +2) Output through the HDMI/MHL/DisplayPort interface + +An I2S/PCM audio channel **shall** be provided on the low speed expansion +interface. + +Other audio facilities are optional. + +DC Power +^^^^^^^^ + +Power **shall** be provided to the board by one (and only one) of the following: + +1) An 8V to 18V power supply from a dedicated DC jack power connector. + A 1.65mm center pin positive DC jack connector, CUI Inc **PJ-041H** or + equivalent, **shall** be placed in the specified location. + +2) An 8V to 18V power supply from the SYS_DCIN pins on the low speed expansion + connector. + +3) A USB Type C port at 5V (if fitted) according to the USB 3.1 specifications. + +The specification does not support multiple simultaneous power supplies +(ie DC jack, mezzanine board power, USB power). If multiple in-specification +supplies are connected there **shall not** be a safety issue and there **shall** +be no damage to the board. + +The board **shall** be able to provide the following power to external devices +when a sufficiently rated power supply is connected to the DC Jack: + + 1) A minimum of 7W to a mezzanine module via the SYS_DCIN line, and + + 2) A minimum of 5W to a mezzanine module via the regulated +5V line, and + + 3) A minimum of 5W to external USB devices connected to the 2 host USB ports, and + + 4) A minimum of 0.18W to a mezzanine module via the regulated +1.8V line + +The board **shall** be able to provide the following power to external devices +when powered from (a) the Expansion connector or from (b) a Type C USB +port (when power does not have to be provided on the SYS_DCIN line) + + 1) A minimum of 5W to a mezzanine module via the regulated +5V line, and + + 2) A minimum of 5W to external USB devices connected to the 2 host USB ports + + 3) A minimum of 0.18W to a mezzanine module via the regulated +1.8V line + +Battery Power and Low Cost Power Supplies +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A board could be powered either by a low cost power supply that is only capable +of providing power for the board and for low power mezzanine boards, or by an +external battery (for example from the SYS_DCIN line or a separate battery +connection). + +Limitations on available power covering the use of smaller and/or +battery power supplies **shall** be clearly documented. + +Measurement, Instrumentation and Testing Facilities +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Boards **shall** support power measurement, instrumentation and testing +facilities. The following facilities **shall** be provided. + +Power Measurement +^^^^^^^^^^^^^^^^^ + +A minimum of 1 current sense resistor **shall** be placed to permit basic +power measurement functions. + + - The total power consumption of the board **shall** be measurable + through a suitable 1% current sense resistor. + + - This **may** be a developer install option (i.e. the sense resistor may + be shipped as a zero ohm resistor for production boards that a developer + can replace for power measurement) + + - The sense resistor **shall** be placed on the main board power supply to + measure the total base board power. It is optional as to whether this will + measure any mezzanine board power usage. + +Additional current sense resistors **may** be placed at the discretion of +the board designer. + +It is **recommended** that additional sense resistors are provided for the main +PMIC downstream supplies to the SoC core, memory etc. + +Current sense resistors shall be made available externally to measurement equipment. One +option for interface is the ARM Energy Probe: + +http://ds.arm.com/ds-5/optimize/arm-energy-probe/ + +The PCB design **shall** provide for low profile male 0.1” header pins to +enable the connection of: + + - The sense resistor connections (2 pins each) + - A single ground pin (for voltage measurement). The Low speed expansion + connector may be documented as being usable for the ground pin requirement. + +This header (or headers) **may** be unpopulated on a retail 96Boards CE board +(enabling users to add the headers themselves). + +Power Button and Reset Button +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The user **shall** be able to manually power up/down and reset the board. +(For example, with one or two button switches). + +It **shall** be possible to connect external switches for power on/off and +for hard reset. + +This **shall** be implemented using the specified pins on the low speed bus +connector (adjacent pins allowing direct connect of a 3 pin connector for +both switches). + +It **shall** be possible to configure the board to power up automatically if +external power is removed and then re-applied. + +This **may** either be default operation or through a configuration option +(e.g. link or switch). + +Implementation note: It is up to the designer how to implement this +functionality. For example, a single push button under SoC/PMIC control could +be used to turn the power on or off, with a long press to carry out a system +reset. In this case the board should automatically always power up when power +is newly applied. Alternatively a physical On/Off toggle switch could be used +to apply power to the board, which would automatically power up when in the On +position. In this case a separate push to reset switch could be implemented. + +External Fan Connection +^^^^^^^^^^^^^^^^^^^^^^^ + +An external fan (for example for a case) connection is available on the low +speed expansion connector by using a 2 pin male header for +5V or +12V fans. + +UART +^^^^ + +One standard UART from the SoC **shall** be made available for general purpose +use on the low speed expansion connector. + +A second UART (TxD/RxD only) **may** be made available on the low speed +expansion connector. + +Note: Off the shelf FTDI 1.8V serial USB cables may be used to interface to +these interfaces. + +JTAG +^^^^ + +JTAG facilities **may** be provided on a board. + +If implemented the JTAG interface **shall** use the 10 pin JTAG connector +(0.05” pitch) +See http://www.support.code-red-tech.com/CodeRedWiki/HardwareDebugConnections + +System and User LEDs +^^^^^^^^^^^^^^^^^^^^ + +The following LEDs **shall** be present on the board. + +The LEDs **shall** be of the specified size, color and location. + +The User LEDs **shall** be directly programmable from the SoC. + + 1) WiFi activity LED - Yellow Type: 0603 SMD + + 2) Bluetooth activity LED - Blue Type: 0603 SMD + + 3) User LEDs x4 - Green Type: 0603 SMD + +Other LEDs and UI interfaces are optional. + +Front Panel and DC Jack Connectors +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Development boards are in general subject to high cycle life of connector +attachments, and should be designed to be as mechanically strong as possible. +Therefore, the front panel connectors (Display, USB Type A and microUSB/USB Type +C) and the DC Jack connector **shall** include through-PCB mechanical support. + +While surface mount electrical connections are acceptable, a fully surface mount +connector without any in/through board mechanical support **shall not** be used. + +Expansion Connectors +^^^^^^^^^^^^^^^^^^^^ + +Two expansion connectors **shall** be provided. The first is a low speed +expansion connector carrying GPIO and other low speed interfaces. The second +is a high speed expansion connector that provides high speed interfaces such +as MIPI DSI, MIPI CSI-2 and MIPI-HSIC. Mezzanine boards are expected to be used +in one of two configurations: + + 1) Low speed expansion connector only + + 2) Low and high speed expansion connectors together + +Low Speed Expansion Connector +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A 40 pin low profile female 2mm receptacle (20x2) 4.5mm height is specified. + +Part numbers include: + + - Molex 87381-4063 (SMT) + - FCI 55510-140LF (SMT) + - Samtec TLE-120-01-G-DV (SMT) + - TE 4-1470209-3 (Through hole) + - TE 4-1734506-3 (Through hole) + - FCI 63453-140LF (Through hole) + +Important notes: + + 1) Unless otherwise indicated the low speed expansion connector signals are + at 1.8V logic levels. + + 2) The mezzanine board connector may be shrouded or unshrouded (see example + part numbers below). Since a shrouded part can be used the connector + footprint should be 43.0x6.5mm with no other components on the board top + side in this area. + +The following interfaces **shall** be available except where specified as +optional: + + - UART0 + - UART1 (optional) + - SPI bus + - I2Cx2 + - I2Sx2 + - GPIO x12 + - Reset and Power button + - 1.8V, 5V and DC_IN power supplies + +Refer to Connector Pin Specification appendix for the required pinout. + +High Speed Expansion Connector +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +A 60 pin 0.8mm high speed Board to Board low profile receptacle connector +is specified. Part numbers include + + - FCI 61082-061409LF + - TE 5177983-2 + +Important note: unless otherwise indicated the high speed expansion connector +signals are at 1.8V logic levels. + +The following interfaces shall be available except where specified as optional: + + - MIPI DSI + - USB + - SD or SPI interface + - MIPI CSI-2 (x2 optional) + - I2C (x2 optional, but 1 shall be provided if CSI interface(s) are provided) + - HSIC (optional) + +Refer to appendix for the required pinout. These connectors have been designed +to provide a board to board separation to a mezzanine board of 7.0 or 8.0mm. + +Expansion Board Connectors +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following mezzanine board connectors may be used to interface to the +baseboard: + + - MOLEX 87831-4029: Low speed 2.5mm mated height (Through hole shrouded) + - FCI 57202-G52-20LF: Low speed 2.5mm mated height (SMT no shroud) + - SAMTEC TMMH-120-01-F: Low speed 2.0mm body (Through hole) + - FCI 61083-063400LF: High speed + - TE 5179030-2: High speed + +Expansion Connector Notes +^^^^^^^^^^^^^^^^^^^^^^^^^ + + 1) GPIO-A **shall** be capable of waking up the SoC from sleep/standby mode + 2) By default all GPIO pins should be configured at boot as inputs to the + SoC. This allows for the mezzanine board configuration to be detected from + the SoC. After the configuration is known GPIO pins (pin-muxed) may be + re-configured in software for mezzanine module specific functions. Through + this mechanism additional support for particular SoC/mezzanine module + configurations may be supported by making the appropriate SoC GPIO special + function pins available on the expansion connector(s). + Note that by default all GPIO pins should be usable as GPIOs (i.e. any + generic mezzanine board may rely on any or all of the specified GPIO pins + being available for use). + 3) A mezzanine board should not place components (other than the required + connectors) on the underside in the area of the base board. + +Standalone Functionality +======================== + +The standalone board requires only a power supply and display connected to +be used as an advanced single board computer (using wireless +keyboard/mouse/WiFi & Bluetooth). + +Maker Functionality +=================== + +The hobby/maker community are able to use the low speed connector directly, +but must be aware that the connections are direct 1.8V level to the on-board +SoC. + +In addition, for this community, CircuitCo Inc. plans to make available an +initial low cost maker mezzanine board that will provide the following +functionality: + + - I/O level shifters to 3.3V/5V + - 0.1” header for easy access to low speed expansion I/O at 3.3/5V levels + - Raspberry Pi compatible CSI camera FFC connector + - Arduino Uno compatible shield interface + - Standard UART connector interface + +This board will connect to any 96Boards CE compliant board. + +Embedded OEM Functionality +========================== + +It is intended that embedded equipment makers can easily create mezzanine boards +that connect to the high speed and low speed connectors to create small form +factor, low profile embedded products. An example would be a LCD panel +interface with touch screen and optional keys/keyboard. Such boards will connect +to any 96Boards CE compliant board. + +Additional Functionality +======================== + +Boards that comply to the 96Boards CE spec may provide additional functionality +provided that all mandatory functionality is available. + +For example a 96Boards CE board could optionally provide facilities such as: + + - Additional custom storage + - Additional I/O - e.g. Ethernet, CANbus etc. + - On board external battery power/charging support for mobile applications + - PCIe interface(s) using PCIe mini or M.2 connectors mounted on the extended + version or on the board underside + +Any included additional functionality, headers, mezzanine or board to board +connectors shall not contravene the 96Boards CE Physical Footprint +specification (including height), or prevent the use of the 96Boards CE low +speed or high speed connector expansion facilities. + +96Boards Consumer Edition Software Requirements +=============================================== + +Unless otherwise stated, support means: + + - Support in the relevant project’s repositories, for example the Linux + kernel git repositories at git.kernel.org + - Source and binary code packages available to download. [#download]_ + +Minimum Software requirements for 96Boards certification will include: + + - Boot architecture (open source implementations are strongly recommended) + + - Support for bootloader such as U-Boot/FDT, UEFI/ACPI, UEFI/FDT + - Support for a secure execution environment (optional) + - Support for ARM Trusted Firmware (ARMv8), including PSCI APIs (optional) + + - Accelerated graphics support + + - Accelerated graphics drivers need to be fully supported either with open + source code, or through royalty free binary drivers. If binary drivers + are utilized, the vendor will provide support to provide updated + drivers/libraries to support new mainline Linux kernel features. + + - Kernel + + - A kernel based on one of the following that is buildable from source code + and any required binary blobs: + + - kernel.org latest “mainline” or “stable” kernel + - The latest Google-supported Android kernel version + - One of the last two kernel.org LTS kernels (for example Linaro LSK) + + - Operating system + The latest released (stable) version of one or more of the following open + source distributions shall be made available for a 96Boards CE compliant + design: + + - Android + - Debian or Ubuntu + - Fedora or Red Hat + - An OpenEmbedded/Yocto build of a Linux distribution + + - Other Operating Systems/Distributions + Other operating systems or distributions may be provided for a 96Boards + product and can be made available to end users on the 96Boards community + portal + +.. [#download] Linaro will provide an open ‘community portal’ for 96Boards + Certified products where users may go for support, software upgrades etc diff --git a/source/chapter3-references.rst b/source/chapter3-references.rst new file mode 100644 index 0000000..f1d114a --- /dev/null +++ b/source/chapter3-references.rst @@ -0,0 +1,17 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +********** +References +********** + +1) CSI - http://mipi.org/specifications/camera-interface + +2) SPI - http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus + +3) DSI - http://mipi.org/specifications/display-interface + +4) MHL - http://www.mhlconsortium.org + +5) DisplayPort - http://www.displayport.org + +6) microSDHC - http://en.wikipedia.org/wiki/Secure_Digital diff --git a/source/chapter4-appendix.rst b/source/chapter4-appendix.rst new file mode 100644 index 0000000..2b6adea --- /dev/null +++ b/source/chapter4-appendix.rst @@ -0,0 +1,506 @@ +.. SPDX-License-Identifier: CC-BY-SA-4.0 + +******** +Appendix +******** + +Expansion Connector Signal Description +====================================== + +40 Pin Low Speed Expansion Connector +------------------------------------ + +2x20 female 2mm header + ++-----------+--------++--------+-----------+ +| GND | Pin 1 || Pin 2 | GND | ++-----------+--------++--------+-----------+ +| UART0_CTS | Pin 3 || Pin 4 | PWR_BTN_N | ++-----------+--------++--------+-----------+ +| UART0_TxD | Pin 5 || Pin 6 | RST_BTN_N | ++-----------+--------++--------+-----------+ +| UART0_RxD | Pin 7 || Pin 8 | SPI0_SCLK | ++-----------+--------++--------+-----------+ +| UART0_RTS | Pin 9 || Pin 10 | SPI0_DIN | ++-----------+--------++--------+-----------+ +| UART0_TxD | Pin 11 || Pin 12 | SPI0_CS | ++-----------+--------++--------+-----------+ +| UART0_RxD | Pin 13 || Pin 14 | SPI0_DOUT | ++-----------+--------++--------+-----------+ +| I2C0_SCL | Pin 15 || Pin 16 | PCM_FS | ++-----------+--------++--------+-----------+ +| I2C0_SDA | Pin 17 || Pin 18 | PCM_CLK | ++-----------+--------++--------+-----------+ +| I2C1_SCL | Pin 19 || Pin 20 | PCM_DO | ++-----------+--------++--------+-----------+ +| I2C1_SDA | Pin 21 || Pin 22 | PCM_DI | ++-----------+--------++--------+-----------+ +| GPIO-A | Pin 23 || Pin 24 | GPIO-B | ++-----------+--------++--------+-----------+ +| GPIO-C | Pin 25 || Pin 26 | GPIO-D | ++-----------+--------++--------+-----------+ +| GPIO-E | Pin 27 || Pin 28 | GPIO-F | ++-----------+--------++--------+-----------+ +| GPIO-G | Pin 29 || Pin 30 | GPIO-H | ++-----------+--------++--------+-----------+ +| GPIO-I | Pin 31 || Pin 32 | GPIO-J | ++-----------+--------++--------+-----------+ +| GPIO-K | Pin 33 || Pin 34 | GPIO-L | ++-----------+--------++--------+-----------+ +| +1V8 | Pin 35 || Pin 36 | SYS_DCIN | ++-----------+--------++--------+-----------+ +| +5V | Pin 37 || Pin 38 | SYS_DCIN | ++-----------+--------++--------+-----------+ +| GND | Pin 39 || Pin 40 | GND | ++-----------+--------++--------+-----------+ + +Pin Descriptions +---------------- + +UART +^^^^ + +One UART **shall** be provided on the low speed expansion bus. + +A second UART **may** be provided + ++------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++============+=========================+======+========+==========+=============+ +| UART0_RxD | Receive serial data | 1.8V | Input | Required | | ++------------+-------------------------+------+--------+----------+-------------+ +| UART0_TxD | Transmit serial data | 1.8V | Output | Required | | ++------------+-------------------------+------+--------+----------+-------------+ +| UART0_RTS | Request to Send control | 1.8V | Output | Required | | ++------------+-------------------------+------+--------+----------+-------------+ +| UART0_CTS | Clear to Send control | 1.8V | Input | Required | | ++------------+-------------------------+------+--------+----------+-------------+ +| UART1_RxD | Receive serial data | 1.8V | Input | Optional | NC | ++------------+-------------------------+------+--------+----------+-------------+ +| UART1_TxD | Transmit serial data | 1.8V | Output | Optional | NC | ++------------+-------------------------+------+--------+----------+-------------+ + +I2C +^^^ + +Two I2C interfaces **shall** be provided on the low speed expansion bus. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| I2C[0-1]_SCL | Serial Clock | 1.8V | OD/PU | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| I2C[0-1]_SDA | Serial Data | 1.8V | OD/PU | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ + +It is **recommended** that a 2K2R pullup is provided on each I2C signal, +dependent on any relevant drive/pullup specifications of the SoC. + +Power and Reset +^^^^^^^^^^^^^^^ + +The following controls **shall** be provided on the low speed expansion bus. + ++--------------+-------------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+===============================+======+========+==========+=============+ +| PWR_BTN_N | Power on/off external request | 1.8V | Input | Required | | ++--------------+-------------------------------+------+--------+----------+-------------+ +| RST_BTN_N | Reset external request | 1.8V | Input | Required | | ++--------------+-------------------------------+------+--------+----------+-------------+ + +These signals **shall** be active low. + +SPI +^^^ + +One SPI bus master **shall** be provided on the low speed expansion bus. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| SPI0_SCLK | Serial Clock | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| SPI0_CS | Chip Select | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| SPI0_DIN | Data In | 1.8V | Input | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| SPI0_DOUT | Data Out | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ + +PCM/I2S +^^^^^^^ + +One PCM/Inter IC Sound (I2S) PCM audio data bus **shall** be provided on the +low speed expansion bus. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| PCM_FS | PCM/I2S Word Clock | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| PCM_CLK | PCM/I2S Bit Clock | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| PCM_DO | PCM/I2S Serial data out | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| PCM_DI | PCM/I2S Serial data in | 1.8V | Input | Required | NC | ++--------------+-------------------------+------+--------+----------+-------------+ + +GPIO +^^^^ + +12 GPIO lines **shall** be provided on the low speed expansion bus. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| GPIO-[A-L] | General Purpose I/O | 1.8V | I/O | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ + +Special functions: +------------------ + +GPIO-A **shall** be capable of waking up the SoC from sleep. +The following pins **shall** have alternate functions for DSI/CSI control if +required by the display/sensor. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| GPIO-F | DSI_BLCTL | 1.8V | Output | | | ++--------------+-------------------------+------+--------+----------+-------------+ +| GPIO-G | DSI_VSYNC | 1.8V | Input | | | ++--------------+-------------------------+------+--------+----------+-------------+ +| GPIO-H | DSI_RST | 1.8V | Output | | | ++--------------+-------------------------+------+--------+----------+-------------+ +| GPIO-I | CSI0_RST | 1.8V | Output | | | ++--------------+-------------------------+------+--------+----------+-------------+ +| GPIO-J | CSI0_PWDN | 1.8V | Output | | | ++--------------+-------------------------+------+--------+----------+-------------+ +| GPIO-K | CSI1_RST | 1.8V | Output | | | ++--------------+-------------------------+------+--------+----------+-------------+ +| GPIO-L | CSI1_PWDN | 1.8V | Output | | | ++--------------+-------------------------+------+--------+----------+-------------+ + +Power Supplies +^^^^^^^^^^^^^^ + +The following power supplies **shall** be provided on the low speed expansion +bus. + ++--------------+---------------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=================================+======+========+==========+=============+ +| +1.8V | 1.8V Power reference (max 0.1A) | 1.8V | Output | Required | | ++--------------+---------------------------------+------+--------+----------+-------------+ +| +5V | 5V System Power Supply | 5V | Power | Required | | ++--------------+---------------------------------+------+--------+----------+-------------+ +| SYS_DCIN | 9-18V Input Power Supply | 12V | Power | Required | | ++--------------+---------------------------------+------+--------+----------+-------------+ + +See the DC Power section of the 96Boards Specification. + +60 Pin High Speed Expansion Connector +------------------------------------- + +0.8mm 50 ohm high speed receptacle + ++--------------------+--------++--------+-----------+ +| SD_DAT0/SPI1_DOUT | Pin 1 || Pin 2 | CSI0_C+ | ++--------------------+--------++--------+-----------+ +| SD_DAT1 | Pin 3 || Pin 4 | CSI0_C- | ++--------------------+--------++--------+-----------+ +| SD_DAT2 | Pin 5 || Pin 6 | GND | ++--------------------+--------++--------+-----------+ +| SD_DAT3/SPI1_CS | Pin 7 || Pin 8 | CSI0_D0+ | ++--------------------+--------++--------+-----------+ +| SD_SCLK/SPI1_SCLK | Pin 9 || Pin 10 | CSI0_D0- | ++--------------------+--------++--------+-----------+ +| SD_CMD/SPI1_DIN | Pin 11 || Pin 12 | GND | ++--------------------+--------++--------+-----------+ +| GND | Pin 13 || Pin 14 | CSI0_D1+ | ++--------------------+--------++--------+-----------+ +| CLK0/CSI0_MCLK | Pin 15 || Pin 16 | CSI0_D1- | ++--------------------+--------++--------+-----------+ +| CLK1/CSI1_MCLK | Pin 17 || Pin 18 | GND | ++--------------------+--------++--------+-----------+ +| GND | Pin 19 || Pin 20 | CSI0_D2+ | ++--------------------+--------++--------+-----------+ +| DSI_CLK+ | Pin 21 || Pin 22 | CSI0_D2- | ++--------------------+--------++--------+-----------+ +| DSI_CLK- | Pin 23 || Pin 24 | GND | ++--------------------+--------++--------+-----------+ +| GND | Pin 25 || Pin 26 | CSI0_D3+ | ++--------------------+--------++--------+-----------+ +| DSI_D0+ | Pin 27 || Pin 28 | CSI0_D3- | ++--------------------+--------++--------+-----------+ +| DSI_D0- | Pin 29 || Pin 30 | GND | ++--------------------+--------++--------+-----------+ +| GND | Pin 31 || Pin 32 | I2C2_SCL | ++--------------------+--------++--------+-----------+ +| DSI_D1+ | Pin 33 || Pin 34 | I2C2_SDA | ++--------------------+--------++--------+-----------+ +| DSI_D1- | Pin 35 || Pin 36 | I2C3_SCL | ++--------------------+--------++--------+-----------+ +| GND | Pin 37 || Pin 38 | I2C3_SDA | ++--------------------+--------++--------+-----------+ +| DSI_D2+ | Pin 39 || Pin 40 | GND | ++--------------------+--------++--------+-----------+ +| DSI_D2- | Pin 41 || Pin 42 | CSI1_D0+ | ++--------------------+--------++--------+-----------+ +| GND | Pin 43 || Pin 44 | CSI1_D0- | ++--------------------+--------++--------+-----------+ +| DSI_D3+ | Pin 45 || Pin 46 | GND | ++--------------------+--------++--------+-----------+ +| DSI_D3- | Pin 47 || Pin 48 | CSI1_D1+ | ++--------------------+--------++--------+-----------+ +| GND | Pin 49 || Pin 50 | CSI1_D1- | ++--------------------+--------++--------+-----------+ +| USB_D+ | Pin 51 || Pin 52 | GND | ++--------------------+--------++--------+-----------+ +| USB_D- | Pin 53 || Pin 54 | CSI1_C+ | ++--------------------+--------++--------+-----------+ +| GND | Pin 55 || Pin 56 | CSI1_C- | ++--------------------+--------++--------+-----------+ +| HSIC_STR | Pin 57 || Pin 58 | GND | ++--------------------+--------++--------+-----------+ +| HSIC_DATA | Pin 59 || Pin 60 | RESERVED | ++--------------------+--------++--------+-----------+ + +Pin Descriptions +---------------- + +MIPI-DSI +^^^^^^^^ + +A MIPI DSI interface **shall** be provided on the high speed expansion bus. + ++----------------+-------------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++================+===============================+======+========+==========+=============+ +| DSI_CLK[+-] | Differential DSI Clock | 1.2V | Output | Required | NC | ++----------------+-------------------------------+------+--------+----------+-------------+ +| DSI_DO[+-] | Differential DSI data channel | 1.2V | IO | Required | NC | ++----------------+-------------------------------+------+--------+----------+-------------+ +| DSI_D[1-3][+-] | Differential DSI data channel | 1.2V | IO | Required | NC | ++----------------+-------------------------------+------+--------+----------+-------------+ + +MIPI-CSI2 +^^^^^^^^^ + +Two MIPI-CSI2 interfaces **may** be provided on the high speed expansion bus. + ++---------------------+-------------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++=====================+===============================+======+========+==========+=============+ +| CSI[0-1]_C[+-] | Differential CSI Clock | 1.2V | Output | Optional | NC | ++---------------------+-------------------------------+------+--------+----------+-------------+ +| CSI[0-1]_D[0-1][+-] | Differential CSI data channel | 1.2V | IO | Optional | NC | ++---------------------+-------------------------------+------+--------+----------+-------------+ +| CSI0_D[2-3][+-] | Differential CSI data channel | 1.2V | IO | Optional | NC | ++---------------------+-------------------------------+------+--------+----------+-------------+ + +I2C +^^^ + +Two I2C interfaces **may** be provided on the high speed expansion bus. + +If one or two CSI2 interfaces are implemented then at least the same number of +I2C interfaces **shall** be provided on the high speed expansion bus. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| I2C[2-3]_SCL | Serial Clock | 1.8V | OD/PU | Required | NC | ++--------------+-------------------------+------+--------+----------+-------------+ +| I2C[2-3]_SDA | Serial Data | 1.8V | OD/PU | Required | NC | ++--------------+-------------------------+------+--------+----------+-------------+ + +It is **recommended** that a 2K2R pullup is provided on each I2C signal, +dependent on any relevant drive/pullup specifications of the SoC. + +HSIC +^^^^ + +One MIPI-HSIC interface **may** be provided on the high speed expansion bus. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| HSIC_STR | HSIC strobe | 1.2V | IO | Optional | NC | ++--------------+-------------------------+------+--------+----------+-------------+ +| HSIC_DATA | HSIC data | 1.2V | IO | Optional | NC | ++--------------+-------------------------+------+--------+----------+-------------+ + +RESERVED +^^^^^^^^ + +One pin **shall** be reserved for future use. It shall be pulled up via 100K +to 1.8V. + ++--------------+-----------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=============================+======+========+==========+=============+ +| RESERVED | Not used, pulled up to 1.8V | 1.8V | N/A | Required | | ++--------------+-----------------------------+------+--------+----------+-------------+ + +SD/SPI +^^^^^^ + +The expansion port **shall** be configured with either an SD port or a +second SPI Port. + +SD Configuration + ++--------------+-------------------------+----------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+==========+========+==========+=============+ +| SD_DAT[0-3] | Serial Data | 3.3/1.8V | IO | Required | | ++--------------+-------------------------+----------+--------+----------+-------------+ +| SD_SCLK | Serial Clock | 3.3/1.8V | Output | Required | | ++--------------+-------------------------+----------+--------+----------+-------------+ +| SD_CMD | Command | 3.3/1.8V | IO | Required | | ++--------------+-------------------------+----------+--------+----------+-------------+ + +SPI Configuration + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| SPI1_SCLK | Serial Clock | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| SPI1_CS | Chip Select | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| SPI1_DIN | Data In | 1.8V | Input | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ +| SPI1_DOUT | Data Out | 1.8V | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ + +CLOCKS +^^^^^^ + +One or two programmable clock interfaces may be provided on the high speed expansion +bus. + ++----------------+--------------------------+----------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++================+==========================+==========+========+==========+=============+ +| CLK0/CSI0_MCLK | SoC Programmable Clock 0 | 1.8V | Output | Optional | NC or GPIO | ++----------------+--------------------------+----------+--------+----------+-------------+ +| CLK1/CSI1_MCLK | SoC Programmable Clock 1 | 1.8V | Output | Optional | NC or GPIO | ++----------------+--------------------------+----------+--------+----------+-------------+ + +If CSI camera(s) are supported on mezzanine boards these clocks **shall** be +available as the CSI reference clocks (in case they are needed). + +USB +^^^ + +One USB host port **shall** be provided on the high speed expansion bus. + ++--------------+-------------------------+------+--------+----------+-------------+ +| Signal | Description | V | Type | Spec. | If not used | ++==============+=========================+======+========+==========+=============+ +| USB_D[+-] | Differential USB data | USB | Output | Required | | ++--------------+-------------------------+------+--------+----------+-------------+ + +In many designs the USB port is expected to come from a USB hub solution +ready for direct connect to a USB interface, therefore these signals are +specified at USB PHY signal levels. + +Single USB port Example +======================= + +On cost-sensitive SoCs targeted at the mobile market there may only be a +single USB 2.x/3.x port on the device. A typical 96Boards USB implementation +needs to implement a USB hub for this situation. This can be achieved in a +number of ways. One example is as follows: + +.. image:: images/usb.png + :alt: USB implementation + +96Boards Consumer Edition +========================= + +2D Reference Drawing +-------------------- + +.. image:: images/96b_ce_std_2x.png + :alt: 96Boards CE Standard Connector + +96Boards Consumer Edition (Extended Version) +============================================ + +The Consumer Edition Extended Version is for those SoCs that require additional +space (typically because of the need for additional memory devices or other +required feature sets). The Extended Version is footprint compatible with the +standard version. + +Board designers have a choice for the extended area (shown in green and top +white above) + +Either: +------- + +Extended A +---------- + +The extended area **shall** conform to the 4mm (except for user links and +thermal management) rules as specified for the main area of the standard +board. The extended rear connector area **shall** conform to the 6.5mm +maximum height. This ensures that the design will work with all 96Boards +program Mezzanine Boards. + +Or: +--- + +Extended B +---------- + +The extended area and the extended rear connector area **shall** use +components that extend to a maximum of 15.0mm above the board surface. Designers +that choose this option have more flexibility in board design for SoC, +component and connector positioning in the extended area, but Large Mezzanine +Boards or Modules (see below) may not be compatible with the board design. + +Additionally, Extended Version boards **may** exceed the underside height +restrictions (for example to mount a hgigh power SoC on the underside of the +board). In this case: + +The board footprint on the underside **shall** be fully documented. + +Standoffs and/or additional heat management **shall** be documented or +provided for when the board is used standalone or in a case. + +2D Reference Drawing (Extended Version) +--------------------------------------- + +.. image:: images/96b_ce_ext_2x.png + :alt: 96Boards CE Extended Connector + +Mezzanine Boards and Modules +============================ + +A mezzanine board or module may be fitted on top of the board. To minimize +product footprint the board has been designed to have a minimal footprint +for a low cost community board. The board to mezzanine module spacing is 7.0mm, +or optionally 8.0mm (depending on the mezzanine module connectors used). + +Mezzanine Boards are defined in two versions. + + - Small Mezzanine Boards or Modules have a maximum area of 85x54mm and do not + exceed the footprint of the 96Boards CE standard board. + + - Large Mezzanine Boards or Modules have no size limit. An example could be + a 12” display module designed to fit directly onto any 96Boards CE design. + +Consideration needs to be given to possible heat build up on the base board +depending on the workload and the board used. Accordingly, provision has been +made for airflow between the base board and mezzanine board by requiring +component heights to be such that a fan can move air across the board between +the base board and the mezzanine. + +Therefore, apart from the connectors to the base board, components **shall not** +be placed on the underside of an mezzanine module design in the footprint area +of the base board. More complete design guidelines for mezzanine boards will be +published at a later date. diff --git a/source/conf.py b/source/conf.py new file mode 100644 index 0000000..6d97e30 --- /dev/null +++ b/source/conf.py @@ -0,0 +1,164 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# 96Boards Consumer Edition specification build configuration file, created by +# sphinx-quickstart on Thu May 10 18:49:38 2018. +# +# This file is execfile()d with the current directory set to its +# containing dir. +# +# Note that not all possible configuration values are present in this +# autogenerated file. +# +# All configuration values have a default; values that are commented out +# serve to show the default. + +# If extensions (or modules to document with autodoc) are in another directory, +# add these directories to sys.path here. If the directory is relative to the +# documentation root, use os.path.abspath to make it absolute, like shown here. +# +# import os +# import sys +# sys.path.insert(0, os.path.abspath('.')) + +import subprocess + +# -- General configuration ------------------------------------------------ + +# If your documentation needs a minimal Sphinx version, state it here. +# +# needs_sphinx = '1.0' + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +extensions = ['sphinx.ext.todo', + 'sphinx.ext.githubpages'] + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates'] + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +# +# source_suffix = ['.rst', '.md'] +source_suffix = '.rst' + +# The master toctree document. +master_doc = 'index' + +# General information about the project. +project = '96Boards Consumer Edition Specification' +copyright = '2015 Linaro Limited' +author = 'Linaro Limited' + +# The version info for the project you're documenting, acts as replacement for +# |version| and |release|, also used in various other places throughout the +# built documents. +# +# The short X.Y version. +try: + version = str(subprocess.check_output(["git", "describe", "--dirty"]), 'utf-8').strip() +except: + version = "unknown-rev" +# The full version, including alpha/beta/rc tags. +release = version + +# The language for content autogenerated by Sphinx. Refer to documentation +# for a list of supported languages. +# +# This is also used if you do content translation via gettext catalogs. +# Usually you set "language" from the command line for these cases. +language = None + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This patterns also effect to html_static_path and html_extra_path +exclude_patterns = [] + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = 'sphinx' + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True + + +# -- Options for HTML output ---------------------------------------------- + +# The theme to use for HTML and HTML Help pages. See the documentation for +# a list of builtin themes. +# +html_theme = 'alabaster' + +# Theme options are theme-specific and customize the look and feel of a theme +# further. For a list of options available for each theme, see the +# documentation. +# +# html_theme_options = {} + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['_static'] + + +# -- Options for HTMLHelp output ------------------------------------------ + +# Output file base name for HTML help builder. +htmlhelp_basename = '96boards-ce-doc' + + +# -- Options for LaTeX output --------------------------------------------- + +latex_elements = { + 'classoptions': ',oneside', + # The paper size ('letterpaper' or 'a4paper'). + # + 'papersize': 'a4paper', + + # The font size ('10pt', '11pt' or '12pt'). + # + # 'pointsize': '10pt', + + # Additional stuff for the LaTeX preamble. + # + # 'preamble': '', + + # Latex figure (float) alignment + # + # 'figure_align': 'htbp', +} + +# Release numbers with a qualifier (ex. '-rc', '-pre') get a watermark. +if '-' in release: + latex_elements['preamble'] = '\\usepackage{draftwatermark}\\SetWatermarkScale{.45}\\SetWatermarkText{%s}' % (release) + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +latex_documents = [ + (master_doc, '96boards-ce.tex', project, author, 'manual'), +] + + +# -- Options for manual page output --------------------------------------- + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + (master_doc, '96boards-ce', project, [author], 1) +] + + +# -- Options for Texinfo output ------------------------------------------- + +# Grouping the document tree into Texinfo files. List of tuples +# (source start file, target name, title, author, +# dir menu entry, description, category) +texinfo_documents = [ + (master_doc, '96boards-ce', project, author, '96Boards Consumer Edition', + 'One line description of project.', 'Miscellaneous'), +] + + + diff --git a/source/images/96b_ce_ext_2x.png b/source/images/96b_ce_ext_2x.png Binary files differnew file mode 100644 index 0000000..5df3460 --- /dev/null +++ b/source/images/96b_ce_ext_2x.png diff --git a/source/images/96b_ce_std_2x.png b/source/images/96b_ce_std_2x.png Binary files differnew file mode 100644 index 0000000..55aff4e --- /dev/null +++ b/source/images/96b_ce_std_2x.png diff --git a/source/images/cc-by-sa-4.0-88x31.eps b/source/images/cc-by-sa-4.0-88x31.eps new file mode 100644 index 0000000..1a8ba84 --- /dev/null +++ b/source/images/cc-by-sa-4.0-88x31.eps @@ -0,0 +1,2727 @@ +%!PS-Adobe-3.0 EPSF-3.0
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%%BeginProlog
%%BeginResource: procset Adobe_level2_AI5 1.2 0 +%%Title: (Adobe Illustrator (R) Version 5.0 Level 2 Emulation) +%%Version: 1.2 0 +%%CreationDate: (04/10/93) () +%%Copyright: ((C) 1987-1996 Adobe Systems Incorporated All Rights Reserved) +userdict /Adobe_level2_AI5 26 dict dup begin + put + /packedarray where not + { + userdict begin + /packedarray + { + array astore readonly + } bind def + /setpacking /pop load def + /currentpacking false def + end + 0 + } if + pop + userdict /defaultpacking currentpacking put true setpacking + /initialize + { + Adobe_level2_AI5 begin + } bind def + /terminate + { + currentdict Adobe_level2_AI5 eq + { + end + } if + } bind def + mark + /setcustomcolor where not + { + /findcmykcustomcolor + { + (AI8_CMYK_CustomColor) + 6 packedarray + } bind def + /findrgbcustomcolor + { + (AI8_RGB_CustomColor) + 5 packedarray + } bind def + /setcustomcolor + { + exch + aload pop dup + (AI8_CMYK_CustomColor) eq + { + pop pop + 4 + { + 4 index mul + 4 1 roll + } repeat + 5 -1 roll pop + setcmykcolor + } + { + dup (AI8_RGB_CustomColor) eq + { + pop pop + 3 + { + 1 exch sub + 3 index mul + 1 exch sub + 3 1 roll + } repeat + 4 -1 roll pop + setrgbcolor + } + { + pop + 4 + { + 4 index mul 4 1 roll + } repeat + 5 -1 roll pop + setcmykcolor + } ifelse + } ifelse + } + def + } if + /setAIseparationgray + { + false setoverprint + 0 setgray + /setseparationgray where{ + pop setseparationgray + }{ + /setcolorspace where{ + pop + [/Separation (All) /DeviceCMYK {dup dup dup}] setcolorspace + 1 exch sub setcolor + }{ + setgray + }ifelse + }ifelse + } def + + /gt38? mark {version cvr cvx exec} stopped {cleartomark true} {38 gt exch pop} ifelse def + userdict /deviceDPI 72 0 matrix defaultmatrix dtransform dup mul exch dup mul add sqrt put + userdict /level2? + systemdict /languagelevel known dup + { + pop systemdict /languagelevel get 2 ge + } if + put +/level2ScreenFreq +{ + begin + 60 + HalftoneType 1 eq + { + pop Frequency + } if + HalftoneType 2 eq + { + pop GrayFrequency + } if + HalftoneType 5 eq + { + pop Default level2ScreenFreq + } if + end +} bind def +userdict /currentScreenFreq + level2? {currenthalftone level2ScreenFreq} {currentscreen pop pop} ifelse put +level2? not + { + /setcmykcolor where not + { + /setcmykcolor + { + exch .11 mul add exch .59 mul add exch .3 mul add + 1 exch sub setgray + } def + } if + /currentcmykcolor where not + { + /currentcmykcolor + { + 0 0 0 1 currentgray sub + } def + } if + /setoverprint where not + { + /setoverprint /pop load def + } if + /selectfont where not + { + /selectfont + { + exch findfont exch + dup type /arraytype eq + { + makefont + } + { + scalefont + } ifelse + setfont + } bind def + } if + /cshow where not + { + /cshow + { + [ + 0 0 5 -1 roll aload pop + ] cvx bind forall + } bind def + } if + } if + cleartomark + /anyColor? + { + add add add 0 ne + } bind def + /testColor + { + gsave + setcmykcolor currentcmykcolor + grestore + } bind def + /testCMYKColorThrough + { + testColor anyColor? + } bind def + userdict /composite? + 1 0 0 0 testCMYKColorThrough + 0 1 0 0 testCMYKColorThrough + 0 0 1 0 testCMYKColorThrough + 0 0 0 1 testCMYKColorThrough + and and and + put + composite? not + { + userdict begin + gsave + /cyan? 1 0 0 0 testCMYKColorThrough def + /magenta? 0 1 0 0 testCMYKColorThrough def + /yellow? 0 0 1 0 testCMYKColorThrough def + /black? 0 0 0 1 testCMYKColorThrough def + grestore + /isCMYKSep? cyan? magenta? yellow? black? or or or def + /customColor? isCMYKSep? not def + end + } if + end defaultpacking setpacking +%%EndResource +%%BeginProcSet: Adobe_ColorImage_AI6 1.3 0 +userdict /Adobe_ColorImage_AI6 known not +{ + userdict /Adobe_ColorImage_AI6 53 dict put +} if +userdict /Adobe_ColorImage_AI6 get begin +/initialize { + Adobe_ColorImage_AI6 begin + Adobe_ColorImage_AI6 { + dup type /arraytype eq { + dup xcheck { + bind + } if + } if + pop pop + } forall +} def +/terminate { end } def +currentdict /Adobe_ColorImage_AI6_Vars known not { + /Adobe_ColorImage_AI6_Vars 41 dict def +} if +Adobe_ColorImage_AI6_Vars begin + /plateindex -1 def + /_newproc null def + /_proc1 null def + /_proc2 null def + /sourcearray 4 array def + /_ptispace null def + /_ptiname null def + /_pti0 0 def + /_pti1 0 def + /_ptiproc null def + /_ptiscale 0 def + /_pticomps 0 def + /_ptibuf 0 string def + /_gtigray 0 def + /_cticmyk null def + /_rtirgb null def + /XIEnable true def + /XIType 0 def + /XIEncoding 0 def + /XICompression 0 def + /XIChannelCount 0 def + /XIBitsPerPixel 0 def + /XIImageHeight 0 def + /XIImageWidth 0 def + /XIImageMatrix null def + /XIRowBytes 0 def + /XIFile null def + /XIBuffer1 null def + /XIBuffer2 null def + /XIBuffer3 null def + /XIDataProc null def + /XIColorSpace /DeviceGray def + /XIColorValues 0 def + /XIPlateList false def +end +/ci6colorimage /colorimage where {/colorimage get}{null} ifelse def +/ci6image systemdict /image get def +/ci6curtransfer systemdict /currenttransfer get def +/ci6curoverprint /currentoverprint where {/currentoverprint get}{{_of}} ifelse def +/ci6foureq { + 4 index ne { + pop pop pop false + }{ + 4 index ne { + pop pop false + }{ + 4 index ne { + pop false + }{ + 4 index eq + } ifelse + } ifelse + } ifelse +} def +/ci6testplate { + Adobe_ColorImage_AI6_Vars begin + /plateindex -1 def + /setcmykcolor where { + pop + gsave + 1 0 0 0 setcmykcolor systemdict /currentgray get exec 1 exch sub + 0 1 0 0 setcmykcolor systemdict /currentgray get exec 1 exch sub + 0 0 1 0 setcmykcolor systemdict /currentgray get exec 1 exch sub + 0 0 0 1 setcmykcolor systemdict /currentgray get exec 1 exch sub + grestore + 1 0 0 0 ci6foureq { + /plateindex 0 def + }{ + 0 1 0 0 ci6foureq { + /plateindex 1 def + }{ + 0 0 1 0 ci6foureq { + /plateindex 2 def + }{ + 0 0 0 1 ci6foureq { + /plateindex 3 def + }{ + 0 0 0 0 ci6foureq { + /plateindex 5 def + } if + } ifelse + } ifelse + } ifelse + } ifelse + pop pop pop pop + } if + plateindex + end +} def +/ci6concatprocs { + /packedarray where { + pop dup type /packedarraytype eq 2 index type + /packedarraytype eq or + }{ + false + } ifelse + { + /_proc2 exch cvlit def + /_proc1 exch cvlit def + _proc1 aload pop + _proc2 aload pop + _proc1 length + _proc2 length add + packedarray cvx + }{ + /_proc2 exch cvlit def + /_proc1 exch cvlit def + /_newproc _proc1 length _proc2 length add array def + _newproc 0 _proc1 putinterval + _newproc _proc1 length _proc2 putinterval + _newproc cvx + } ifelse +} def +/ci6istint { + type /arraytype eq +} def +/ci6isspot { + dup type /arraytype eq { + dup length 1 sub get /Separation eq + }{ + pop false + } ifelse +} def +/ci6spotname { + dup ci6isspot {dup length 2 sub get}{pop ()} ifelse +} def +/ci6altspace { + aload pop pop pop ci6colormake +} def +/ci6numcomps { + dup /DeviceGray eq { + pop 1 + }{ + dup /DeviceRGB eq { + pop 3 + }{ + /DeviceCMYK eq { + 4 + }{ + 1 + } ifelse + } ifelse + } ifelse +} def +/ci6marksplate { + dup /DeviceGray eq { + pop plateindex 3 eq + }{ + dup /DeviceRGB eq { + pop plateindex 5 ne + }{ + dup /DeviceCMYK eq { + pop plateindex 5 ne + }{ + dup ci6isspot { + /findcmykcustomcolor where { + pop + dup length 2 sub get + 0.1 0.1 0.1 0.1 5 -1 roll + findcmykcustomcolor 1 setcustomcolor + systemdict /currentgray get exec + 1 ne + }{ + pop plateindex 5 ne + } ifelse + }{ + pop plateindex 5 ne + } ifelse + } ifelse + } ifelse + } ifelse +} def +/ci6colormake { + dup ci6numcomps + exch 1 index 2 add 1 roll + dup 1 eq {pop}{array astore} ifelse + exch +} def +/ci6colorexpand { + dup ci6spotname exch + dup ci6istint { + ci6altspace + exch 4 1 roll + }{ + 1 3 1 roll + } ifelse +} def +/ci6colortint { + dup /DeviceGray eq { + 3 1 roll 1 exch sub mul 1 exch sub exch + }{ + dup /DeviceRGB eq { + 3 1 roll {1 exch sub 1 index mul 1 exch sub exch} forall pop 3 array astore exch + }{ + dup /DeviceCMYK eq { + 3 1 roll {1 index mul exch} forall pop 4 array astore exch + }{ + 3 1 roll mul exch + } ifelse + } ifelse + } ifelse +} def +/ci6colortocmyk { + dup /DeviceGray eq { + pop 1 exch sub 0 0 0 4 -1 roll 4 array astore + }{ + dup /DeviceRGB eq { + pop aload pop _rgbtocmyk 4 array astore + }{ + dup /DeviceCMYK eq { + pop + }{ + ci6altspace ci6colortint ci6colortocmyk + } ifelse + } ifelse + } ifelse +} def +/ci6makeimagedict { + 7 dict begin + /ImageType 1 def + /Decode exch def + /DataSource exch def + /ImageMatrix exch def + /BitsPerComponent exch def + /Height exch def + /Width exch def + currentdict end +} def +/ci6stringinvert { + 0 1 2 index length 1 sub { + dup 2 index exch get 255 exch sub 2 index 3 1 roll put + } for +} def +/ci6stringknockout { + 0 1 2 index length 1 sub { + 255 2 index 3 1 roll put + } for +} def +/ci6stringapply { + 0 1 4 index length 1 sub { + dup + 4 index exch get + 3 index 3 1 roll + 3 index exec + } for + pop exch pop +} def +/ci6walkrgbstring { + 0 3 index + dup length 1 sub 0 3 3 -1 roll { + 3 getinterval {} forall + 5 index exec + 3 index + } for + + 5 {pop} repeat +} def +/ci6walkcmykstring +{ + 0 3 index + dup length 1 sub 0 4 3 -1 roll { + 4 getinterval {} forall + + 6 index exec + + 3 index + + } for + + 5 { pop } repeat + +} def +/ci6putrgbtograystr +{ + .11 mul exch + + .59 mul add exch + + .3 mul add + + cvi 3 copy put + + pop 1 add +} def +/ci6putcmyktograystr +{ + exch .11 mul add + + exch .59 mul add + + exch .3 mul add + + dup 255 gt { pop 255 } if + + 255 exch sub cvi 3 copy put + + pop 1 add +} def +/ci6rgbtograyproc { + Adobe_ColorImage_AI6_Vars begin + sourcearray 0 get exec + XIBuffer3 + dup 3 1 roll + + /ci6putrgbtograystr load exch + ci6walkrgbstring + end +} def +/ci6cmyktograyproc { + Adobe_ColorImage_AI6_Vars begin + sourcearray 0 get exec + XIBuffer3 + dup 3 1 roll + + /ci6putcmyktograystr load exch + ci6walkcmykstring + end +} def +/ci6separatecmykproc { + Adobe_ColorImage_AI6_Vars begin + sourcearray 0 get exec + + XIBuffer3 + + 0 2 index + + plateindex 4 2 index length 1 sub { + get 255 exch sub + + 3 copy put pop 1 add + + 2 index + } for + pop pop exch pop + end +} def + +/ci6compositeimage { + dup 1 eq { + pop pop image + }{ + /ci6colorimage load null ne { + ci6colorimage + }{ + 3 1 roll pop + sourcearray 0 3 -1 roll put + 3 eq {/ci6rgbtograyproc}{/ci6cmyktograyproc} ifelse load + image + } ifelse + } ifelse +} def +/ci6knockoutimage { + gsave + 0 ci6curtransfer exec 1 ci6curtransfer exec + eq { + 0 ci6curtransfer exec 0.5 lt + }{ + 0 ci6curtransfer exec 1 ci6curtransfer exec gt + } ifelse + {{pop 0}}{{pop 1}} ifelse + systemdict /settransfer get exec + ci6compositeimage + grestore +} def +/ci6drawimage { + ci6testplate -1 eq { + pop ci6compositeimage + }{ + dup type /arraytype eq { + dup length plateindex gt {plateindex get}{pop false} ifelse + }{ + { + true + }{ + dup 1 eq {plateindex 3 eq}{plateindex 3 le} ifelse + } ifelse + } ifelse + { + dup 1 eq { + pop pop ci6image + }{ + dup 3 eq { + ci6compositeimage + }{ + pop pop + sourcearray 0 3 -1 roll put + /ci6separatecmykproc load + ci6image + } ifelse + } ifelse + }{ + ci6curoverprint { + 7 {pop} repeat + }{ + ci6knockoutimage + } ifelse + } ifelse + } ifelse +} def +/ci6proctintimage { + /_ptispace exch store /_ptiname exch store /_pti1 exch store /_pti0 exch store /_ptiproc exch store + /_pticomps _ptispace ci6numcomps store + /_ptiscale _pti1 _pti0 sub store + level2? { + _ptiname length 0 gt version cvr 2012 ge and { + [/Separation _ptiname _ptispace {_ptiproc}] setcolorspace + [_pti0 _pti1] ci6makeimagedict ci6image + }{ + [/Indexed _ptispace 255 {255 div _ptiscale mul _pti0 add _ptiproc}] setcolorspace + [0 255] ci6makeimagedict ci6image + } ifelse + }{ + _pticomps 1 eq { + { + dup + { + 255 div _ptiscale mul _pti0 add _ptiproc 255 mul cvi put + } ci6stringapply + } ci6concatprocs ci6image + }{ + { + dup length _pticomps mul dup _ptibuf length ne {/_ptibuf exch string store}{pop} ifelse + _ptibuf { + exch _pticomps mul exch 255 div _ptiscale mul _pti0 add _ptiproc + _pticomps 2 add -2 roll + _pticomps 1 sub -1 0 { + 1 index add 2 index exch + 5 -1 roll + 255 mul cvi put + } for + pop pop + } ci6stringapply + } ci6concatprocs false _pticomps + /ci6colorimage load null eq {7 {pop} repeat}{ci6colorimage} ifelse + } ifelse + } ifelse +} def +/ci6graytintimage { + /_gtigray 5 -1 roll store + {1 _gtigray sub mul 1 exch sub} 4 1 roll + /DeviceGray ci6proctintimage +} def +/ci6cmyktintimage { + /_cticmyk 5 -1 roll store + {_cticmyk {1 index mul exch} forall pop} 4 1 roll + /DeviceCMYK ci6proctintimage +} def +/ci6rgbtintimage { + /_rtirgb 5 -1 roll store + {_rtirgb {1 exch sub 1 index mul 1 exch sub exch} forall pop} 4 1 roll + /DeviceRGB ci6proctintimage +} def +/ci6tintimage { + ci6testplate -1 eq { + ci6colorexpand + 3 -1 roll 5 -1 roll {0}{0 exch} ifelse 4 2 roll + dup /DeviceGray eq { + pop ci6graytintimage + }{ + dup /DeviceRGB eq { + pop ci6rgbtintimage + }{ + pop ci6cmyktintimage + } ifelse + } ifelse + }{ + dup ci6marksplate { + plateindex 5 lt { + ci6colortocmyk plateindex get + dup 0 eq ci6curoverprint and { + 7 {pop} repeat + }{ + 1 exch sub + exch {1 0}{0 1} ifelse () ci6graytintimage + } ifelse + }{ + pop exch {0}{0 exch} ifelse 0 3 1 roll () ci6graytintimage + } ifelse + }{ + ci6curoverprint { + 8 {pop} repeat + }{ + pop pop pop + {pop 1} 0 1 () /DeviceGray ci6proctintimage + } ifelse + } ifelse + } ifelse +} def +/XINullImage { +} def +/XIImageMask { + XIImageWidth XIImageHeight false + [XIImageWidth 0 0 XIImageHeight neg 0 0] + /XIDataProc load + imagemask +} def +/XIImageTint { + XIImageWidth XIImageHeight XIBitsPerPixel + [XIImageWidth 0 0 XIImageHeight neg 0 0] + /XIDataProc load + XIType 3 eq XIColorValues XIColorSpace ci6tintimage +} def +/XIImage { + XIImageWidth XIImageHeight XIBitsPerPixel + [XIImageWidth 0 0 XIImageHeight neg 0 0] + /XIDataProc load + false XIChannelCount XIPlateList ci6drawimage +} def +/XG { + pop pop +} def +/XF { + 13 {pop} repeat +} def +/Xh { + Adobe_ColorImage_AI6_Vars begin + gsave + /XIType exch def + /XIImageHeight exch def + /XIImageWidth exch def + /XIImageMatrix exch def + 0 0 moveto + XIImageMatrix concat + XIImageWidth XIImageHeight scale + + /_lp /null ddef + _fc + /_lp /imagemask ddef + end +} def +/XH { + Adobe_ColorImage_AI6_Vars begin + grestore + end +} def +/XIEnable { + Adobe_ColorImage_AI6_Vars /XIEnable 3 -1 roll put +} def +/XC { + Adobe_ColorImage_AI6_Vars begin + ci6colormake + /XIColorSpace exch def + /XIColorValues exch def + end +} def +/XIPlates { + Adobe_ColorImage_AI6_Vars begin + /XIPlateList exch def + end +} def +/XI +{ + Adobe_ColorImage_AI6_Vars begin + gsave + /XIType exch def + cvi dup + 256 idiv /XICompression exch store + 256 mod /XIEncoding exch store + pop pop + /XIChannelCount exch def + /XIBitsPerPixel exch def + /XIImageHeight exch def + /XIImageWidth exch def + pop pop pop pop + /XIImageMatrix exch def + XIBitsPerPixel 1 eq { + XIImageWidth 8 div ceiling cvi + }{ + XIImageWidth XIChannelCount mul + } ifelse + /XIRowBytes exch def + XIEnable { + /XIBuffer3 XIImageWidth string def + XICompression 0 eq { + /XIBuffer1 XIRowBytes string def + XIEncoding 0 eq { + {currentfile XIBuffer1 readhexstring pop} + }{ + {currentfile XIBuffer1 readstring pop} + } ifelse + }{ + /XIBuffer1 256 string def + /XIBuffer2 XIRowBytes string def + {currentfile XIBuffer1 readline pop (%) anchorsearch {pop} if} + /ASCII85Decode filter /DCTDecode filter + /XIFile exch def + {XIFile XIBuffer2 readstring pop} + } ifelse + /XIDataProc exch def + + XIType 1 ne { + 0 setgray + } if + XIType 1 eq { + XIImageMask + }{ + XIType 2 eq XIType 3 eq or { + XIImageTint + }{ + XIImage + } ifelse + } ifelse + }{ + XINullImage + } ifelse + /XIPlateList false def + grestore + end +} def +end +%%EndProcSet +%%BeginResource: procset Adobe_Illustrator_AI5 1.3 0 +%%Title: (Adobe Illustrator (R) Version 8.0 Full Prolog) +%%Version: 1.3 0 +%%CreationDate: (3/7/1994) () +%%Copyright: ((C) 1987-1998 Adobe Systems Incorporated All Rights Reserved) +currentpacking true setpacking +userdict /Adobe_Illustrator_AI5_vars 112 dict dup begin +put +/_?cmyk false def +/_eo false def +/_lp /none def +/_pf +{ +} def +/_ps +{ +} def +/_psf +{ +} def +/_pss +{ +} def +/_pjsf +{ +} def +/_pjss +{ +} def +/_pola 0 def +/_doClip 0 def +/cf currentflat def +/_lineorientation 0 def +/_charorientation 0 def +/_yokoorientation 0 def +/_tm matrix def +/_renderStart +[ +/e0 /r0 /a0 /o0 /e1 /r1 /a1 /i0 +] def +/_renderEnd +[ +null null null null /i1 /i1 /i1 /i1 +] def +/_render -1 def +/_shift [0 0] def +/_ax 0 def +/_ay 0 def +/_cx 0 def +/_cy 0 def +/_leading +[ +0 0 +] def +/_ctm matrix def +/_mtx matrix def +/_sp 16#020 def +/_hyphen (-) def +/_fontSize 0 def +/_fontAscent 0 def +/_fontDescent 0 def +/_fontHeight 0 def +/_fontRotateAdjust 0 def +/Ss 256 string def +Ss 0 (fonts/) putinterval +/_cnt 0 def +/_scale [1 1] def +/_nativeEncoding 0 def +/_useNativeEncoding 0 def +/_tempEncode 0 def +/_pntr 0 def +/_tDict 2 dict def +/_hfname 100 string def +/_hffound false def +/Tx +{ +} def +/Tj +{ +} def +/CRender +{ +} def +/_AI3_savepage +{ +} def +/_gf null def +/_cf 4 array def +/_rgbf 3 array def +/_if null def +/_of false def +/_fc +{ +} def +/_gs null def +/_cs 4 array def +/_rgbs 3 array def +/_is null def +/_os false def +/_sc +{ +} def +/_pd 1 dict def +/_ed 15 dict def +/_pm matrix def +/_fm null def +/_fd null def +/_fdd null def +/_sm null def +/_sd null def +/_sdd null def +/_i null def +/_lobyte 0 def +/_hibyte 0 def +/_cproc null def +/_cscript 0 def +/_hvax 0 def +/_hvay 0 def +/_hvwb 0 def +/_hvcx 0 def +/_hvcy 0 def +/_bitfont null def +/_bitlobyte 0 def +/_bithibyte 0 def +/_bitkey null def +/_bitdata null def +/_bitindex 0 def +/discardSave null def +/buffer 256 string def +/beginString null def +/endString null def +/endStringLength null def +/layerCnt 1 def +/layerCount 1 def +/perCent (%) 0 get def +/perCentSeen? false def +/newBuff null def +/newBuffButFirst null def +/newBuffLast null def +/clipForward? false def +end +userdict /Adobe_Illustrator_AI5 known not { + userdict /Adobe_Illustrator_AI5 100 dict put +} if +userdict /Adobe_Illustrator_AI5 get begin +/initialize +{ + Adobe_Illustrator_AI5 dup begin + Adobe_Illustrator_AI5_vars begin + /_aicmykps where {pop /_?cmyk _aicmykps def}if + discardDict + { + bind pop pop + } forall + dup /nc get begin + { + dup xcheck 1 index type /operatortype ne and + { + bind + } if + pop pop + } forall + end + newpath +} def +/terminate +{ + end + end +} def +/_ +null def +/ddef +{ + Adobe_Illustrator_AI5_vars 3 1 roll put +} def +/xput +{ + dup load dup length exch maxlength eq + { + dup dup load dup + length 2 mul dict copy def + } if + load begin + def + end +} def +/npop +{ + { + pop + } repeat +} def +/hswj +{ + dup stringwidth 3 2 roll + { + _hvwb eq { exch _hvcx add exch _hvcy add } if + exch _hvax add exch _hvay add + } cforall +} def +/vswj +{ + 0 0 3 -1 roll + { + dup 255 le + _charorientation 1 eq + and + { + dup cstring stringwidth 5 2 roll + _hvwb eq { exch _hvcy sub exch _hvcx sub } if + exch _hvay sub exch _hvax sub + 4 -1 roll sub exch + 3 -1 roll sub exch + } + { + _hvwb eq { exch _hvcy sub exch _hvcx sub } if + exch _hvay sub exch _hvax sub + _fontHeight sub + } ifelse + } cforall +} def +/swj +{ + 6 1 roll + /_hvay exch ddef + /_hvax exch ddef + /_hvwb exch ddef + /_hvcy exch ddef + /_hvcx exch ddef + _lineorientation 0 eq { hswj } { vswj } ifelse +} def +/sw +{ + 0 0 0 6 3 roll swj +} def +/vjss +{ + 4 1 roll + { + dup cstring + dup length 1 eq + _charorientation 1 eq + and + { + -90 rotate + currentpoint + _fontRotateAdjust add + moveto + gsave + false charpath currentpoint + 5 index setmatrix stroke + grestore + _fontRotateAdjust sub + moveto + _sp eq + { + 5 index 5 index rmoveto + } if + 2 copy rmoveto + 90 rotate + } + { + currentpoint + _fontHeight sub + 5 index sub + 3 index _sp eq + { + 9 index sub + } if + + currentpoint + exch 4 index stringwidth pop 2 div sub + exch _fontAscent sub + moveto + + gsave + 2 index false charpath + 6 index setmatrix stroke + grestore + + moveto pop pop + } ifelse + } cforall + 6 npop +} def +/hjss +{ + 4 1 roll + { + dup cstring + gsave + false charpath currentpoint + 5 index setmatrix stroke + grestore + moveto + _sp eq + { + 5 index 5 index rmoveto + } if + 2 copy rmoveto + } cforall + 6 npop +} def +/jss +{ + _lineorientation 0 eq { hjss } { vjss } ifelse +} def +/ss +{ + 0 0 0 7 3 roll jss +} def +/vjsp +{ + 4 1 roll + { + dup cstring + dup length 1 eq + _charorientation 1 eq + and + { + -90 rotate + currentpoint + _fontRotateAdjust add + moveto + false charpath + currentpoint + _fontRotateAdjust sub + moveto + _sp eq + { + 5 index 5 index rmoveto + } if + 2 copy rmoveto + 90 rotate + } + { + currentpoint + _fontHeight sub + 5 index sub + 3 index _sp eq + { + 9 index sub + } if + + currentpoint + exch 4 index stringwidth pop 2 div sub + exch _fontAscent sub + moveto + + 2 index false charpath + + moveto pop pop + } ifelse + } cforall + 6 npop +} def +/hjsp +{ + 4 1 roll + { + dup cstring + false charpath + _sp eq + { + 5 index 5 index rmoveto + } if + 2 copy rmoveto + } cforall + 6 npop +} def +/jsp +{ + matrix currentmatrix + _lineorientation 0 eq {hjsp} {vjsp} ifelse +} def +/sp +{ + matrix currentmatrix + 0 0 0 7 3 roll + _lineorientation 0 eq {hjsp} {vjsp} ifelse +} def +/pl +{ + transform + 0.25 sub round 0.25 add exch + 0.25 sub round 0.25 add exch + itransform +} def +/setstrokeadjust where +{ + pop true setstrokeadjust + /c + { + curveto + } def + /C + /c load def + /v + { + currentpoint 6 2 roll curveto + } def + /V + /v load def + /y + { + 2 copy curveto + } def + /Y + /y load def + /l + { + lineto + } def + /L + /l load def + /m + { + moveto + } def +} +{ + /c + { + pl curveto + } def + /C + /c load def + /v + { + currentpoint 6 2 roll pl curveto + } def + /V + /v load def + /y + { + pl 2 copy curveto + } def + /Y + /y load def + /l + { + pl lineto + } def + /L + /l load def + /m + { + pl moveto + } def +} ifelse +/d +{ + setdash +} def +/cf +{ +} def +/i +{ + dup 0 eq + { + pop cf + } if + setflat +} def +/j +{ + setlinejoin +} def +/J +{ + setlinecap +} def +/M +{ + setmiterlimit +} def +/w +{ + setlinewidth +} def +/XR +{ + 0 ne + /_eo exch ddef +} def +/H +{ +} def +/h +{ + closepath +} def +/N +{ + _pola 0 eq + { + _doClip 1 eq + { + _eo {eoclip} {clip} ifelse /_doClip 0 ddef + } if + newpath + } + { + /CRender + { + N + } ddef + } ifelse +} def +/n +{ + N +} def +/F +{ + _pola 0 eq + { + _doClip 1 eq + { + gsave _pf grestore _eo {eoclip} {clip} ifelse newpath /_lp /none ddef _fc + /_doClip 0 ddef + } + { + _pf + } ifelse + } + { + /CRender + { + F + } ddef + } ifelse +} def +/f +{ + closepath + F +} def +/S +{ + _pola 0 eq + { + _doClip 1 eq + { + gsave _ps grestore _eo {eoclip} {clip} ifelse newpath /_lp /none ddef _sc + /_doClip 0 ddef + } + { + _ps + } ifelse + } + { + /CRender + { + S + } ddef + } ifelse +} def +/s +{ + closepath + S +} def +/B +{ + _pola 0 eq + { + _doClip 1 eq + gsave F grestore + { + gsave S grestore _eo {eoclip} {clip} ifelse newpath /_lp /none ddef _sc + /_doClip 0 ddef + } + { + S + } ifelse + } + { + /CRender + { + B + } ddef + } ifelse +} def +/b +{ + closepath + B +} def +/W +{ + /_doClip 1 ddef +} def +/* +{ + count 0 ne + { + dup type /stringtype eq + { + pop + } if + } if + newpath +} def +/u +{ +} def +/U +{ +} def +/q +{ + _pola 0 eq + { + gsave + } if +} def +/Q +{ + _pola 0 eq + { + grestore + } if +} def +/*u +{ + _pola 1 add /_pola exch ddef +} def +/*U +{ + _pola 1 sub /_pola exch ddef + _pola 0 eq + { + CRender + } if +} def +/D +{ + pop +} def +/*w +{ +} def +/*W +{ +} def +/` +{ + /_i save ddef + clipForward? + { + nulldevice + } if + 6 1 roll 4 npop + concat pop + userdict begin + /showpage + { + } def + 0 setgray + 0 setlinecap + 1 setlinewidth + 0 setlinejoin + 10 setmiterlimit + [] 0 setdash + /setstrokeadjust where {pop false setstrokeadjust} if + newpath + 0 setgray + false setoverprint +} def +/~ +{ + end + _i restore +} def +/_rgbtocmyk +{ + 3 + { + 1 exch sub 3 1 roll + } repeat + 3 copy 1 4 1 roll + 3 + { + 3 index 2 copy gt + { + exch + } if + pop 4 1 roll + } repeat + pop pop pop + 4 1 roll + 3 + { + 3 index sub + 3 1 roll + } repeat + 4 -1 roll +} def +/setrgbfill +{ + _rgbf astore pop + /_fc + { + _lp /fill ne + { + _of setoverprint + _rgbf aload pop setrgbcolor + /_lp /fill ddef + } if + } ddef + /_pf + { + _fc + _eo {eofill} {fill} ifelse + } ddef + /_psf + { + _fc + hvashow + } ddef + /_pjsf + { + _fc + hvawidthshow + } ddef + /_lp /none ddef +} def +/setrgbstroke +{ + _rgbs astore pop + /_sc + { + _lp /stroke ne + { + _os setoverprint + _rgbs aload pop setrgbcolor + /_lp /stroke ddef + } if + } ddef + /_ps + { + _sc + stroke + } ddef + /_pss + { + _sc + ss + } ddef + /_pjss + { + _sc + jss + } ddef + /_lp /none ddef +} def +/O +{ + 0 ne + /_of exch ddef + /_lp /none ddef +} def +/R +{ + 0 ne + /_os exch ddef + /_lp /none ddef +} def +/g +{ + /_gf exch ddef + /_fc + { + _lp /fill ne + { + _of setoverprint + _gf setgray + /_lp /fill ddef + } if + } ddef + /_pf + { + _fc + _eo {eofill} {fill} ifelse + } ddef + /_psf + { + _fc + hvashow + } ddef + /_pjsf + { + _fc + hvawidthshow + } ddef + /_lp /none ddef +} def +/G +{ + /_gs exch ddef + /_sc + { + _lp /stroke ne + { + _os setoverprint + _gs setgray + /_lp /stroke ddef + } if + } ddef + /_ps + { + _sc + stroke + } ddef + /_pss + { + _sc + ss + } ddef + /_pjss + { + _sc + jss + } ddef + /_lp /none ddef +} def +/k +{ + _cf astore pop + /_fc + { + _lp /fill ne + { + _of setoverprint + _cf aload pop setcmykcolor + /_lp /fill ddef + } if + } ddef + /_pf + { + _fc + _eo {eofill} {fill} ifelse + } ddef + /_psf + { + _fc + hvashow + } ddef + /_pjsf + { + _fc + hvawidthshow + } ddef + /_lp /none ddef +} def +/K +{ + _cs astore pop + /_sc + { + _lp /stroke ne + { + _os setoverprint + _cs aload pop setcmykcolor + /_lp /stroke ddef + } if + } ddef + /_ps + { + _sc + stroke + } ddef + /_pss + { + _sc + ss + } ddef + /_pjss + { + _sc + jss + } ddef + /_lp /none ddef +} def +/Xa +{ + _?cmyk { + 3 npop k + }{ + setrgbfill 4 npop + } ifelse +} def +/XA +{ + _?cmyk { + 3 npop K + }{ + setrgbstroke 4 npop + } ifelse +} def +/Xs +{ + /_gf exch ddef + 5 npop + /_fc + { + _lp /fill ne + { + _of setoverprint + _gf setAIseparationgray + /_lp /fill ddef + } if + } ddef + /_pf + { + _fc + _eo {eofill} {fill} ifelse + } ddef + /_psf + { + _fc + hvashow + } ddef + /_pjsf + { + _fc + hvawidthshow + } ddef + /_lp /none ddef +} def +/XS +{ + /_gs exch ddef + 5 npop + /_sc + { + _lp /stroke ne + { + _os setoverprint + _gs setAIseparationgray + /_lp /stroke ddef + } if + } ddef + /_ps + { + _sc + stroke + } ddef + /_pss + { + _sc + ss + } ddef + /_pjss + { + _sc + jss + } ddef + /_lp /none ddef +} def +/Xx +{ + exch + /_gf exch ddef + 0 eq { + findcmykcustomcolor + }{ + _?cmyk {true}{/findrgbcustomcolor where{pop false}{true}ifelse}ifelse + { + 4 1 roll 3 npop + findcmykcustomcolor + }{ + 8 -4 roll 4 npop + findrgbcustomcolor + } ifelse + } ifelse + /_if exch ddef + /_fc + { + _lp /fill ne + { + _of setoverprint + _if _gf 1 exch sub setcustomcolor + /_lp /fill ddef + } if + } ddef + /_pf + { + _fc + _eo {eofill} {fill} ifelse + } ddef + /_psf + { + _fc + hvashow + } ddef + /_pjsf + { + _fc + hvawidthshow + } ddef + /_lp /none ddef +} def +/XX +{ + exch + /_gs exch ddef + 0 eq { + findcmykcustomcolor + }{ + _?cmyk {true}{/findrgbcustomcolor where{pop false}{true}ifelse}ifelse + { + 4 1 roll 3 npop + findcmykcustomcolor + }{ + 8 -4 roll 4 npop + findrgbcustomcolor + } ifelse + } ifelse + /_is exch ddef + /_sc + { + _lp /stroke ne + { + _os setoverprint + _is _gs 1 exch sub setcustomcolor + /_lp /stroke ddef + } if + } ddef + /_ps + { + _sc + stroke + } ddef + /_pss + { + _sc + ss + } ddef + /_pjss + { + _sc + jss + } ddef + /_lp /none ddef +} def +/x +{ + /_gf exch ddef + findcmykcustomcolor + /_if exch ddef + /_fc + { + _lp /fill ne + { + _of setoverprint + _if _gf 1 exch sub setcustomcolor + /_lp /fill ddef + } if + } ddef + /_pf + { + _fc + _eo {eofill} {fill} ifelse + } ddef + /_psf + { + _fc + hvashow + } ddef + /_pjsf + { + _fc + hvawidthshow + } ddef + /_lp /none ddef +} def +/X +{ + /_gs exch ddef + findcmykcustomcolor + /_is exch ddef + /_sc + { + _lp /stroke ne + { + _os setoverprint + _is _gs 1 exch sub setcustomcolor + /_lp /stroke ddef + } if + } ddef + /_ps + { + _sc + stroke + } ddef + /_pss + { + _sc + ss + } ddef + /_pjss + { + _sc + jss + } ddef + /_lp /none ddef +} def +/XK +{ + 3 -1 roll pop + 0 eq + { + 1 exch sub + 3 {dup 3 1 roll mul 5 1 roll} repeat + mul 4 1 roll + K + } + { + 1 exch sub 4 1 roll + 3 {1 exch sub 3 index mul 1 exch sub 3 1 roll} repeat + 4 -1 roll pop + XA + } ifelse +} def +/Xk +{ + 3 -1 roll pop + 0 eq + { + 1 exch sub + 3 {dup 3 1 roll mul 5 1 roll} repeat + mul 4 1 roll + k + } + { + 1 exch sub 4 1 roll + 3 {1 exch sub 3 index mul 1 exch sub 3 1 roll} repeat + 4 -1 roll pop + Xa + } ifelse +} def +/A +{ + pop +} def +/annotatepage +{ +userdict /annotatepage 2 copy known {get exec} {pop pop} ifelse +} def +/XT { + pop pop +} def +/Xt { + pop +} def +/discard +{ + save /discardSave exch store + discardDict begin + /endString exch store + gt38? + { + 2 add + } if + load + stopped + pop + end + discardSave restore +} bind def +userdict /discardDict 7 dict dup begin +put +/pre38Initialize +{ + /endStringLength endString length store + /newBuff buffer 0 endStringLength getinterval store + /newBuffButFirst newBuff 1 endStringLength 1 sub getinterval store + /newBuffLast newBuff endStringLength 1 sub 1 getinterval store +} def +/shiftBuffer +{ + newBuff 0 newBuffButFirst putinterval + newBuffLast 0 + currentfile read not + { + stop + } if + put +} def +0 +{ + pre38Initialize + mark + currentfile newBuff readstring exch pop + { + { + newBuff endString eq + { + cleartomark stop + } if + shiftBuffer + } loop + } + { + stop + } ifelse +} def +1 +{ + pre38Initialize + /beginString exch store + mark + currentfile newBuff readstring exch pop + { + { + newBuff beginString eq + { + /layerCount dup load 1 add store + } + { + newBuff endString eq + { + /layerCount dup load 1 sub store + layerCount 0 eq + { + cleartomark stop + } if + } if + } ifelse + shiftBuffer + } loop + } if +} def +2 +{ + mark + { + currentfile buffer {readline} stopped { + % assume error was due to overfilling the buffer + }{ + not + { + stop + } if + endString eq { + cleartomark stop + } if + }ifelse + } loop +} def +3 +{ + /beginString exch store + /layerCnt 1 store + mark + { + currentfile buffer {readline} stopped { + % assume error was due to overfilling the buffer + }{ + not + { + stop + } if + dup beginString eq + { + pop /layerCnt dup load 1 add store + } + { + endString eq + { + layerCnt 1 eq + { + cleartomark stop + } + { + /layerCnt dup load 1 sub store + } ifelse + } if + } ifelse + }ifelse + } loop +} def +end +userdict /clipRenderOff 15 dict dup begin +put +{ + /n /N /s /S /f /F /b /B +} +{ + { + _doClip 1 eq + { + /_doClip 0 ddef _eo {eoclip} {clip} ifelse + } if + newpath + } def +} forall +/Tr /pop load def +/Bb {} def +/BB /pop load def +/Bg {12 npop} def +/Bm {6 npop} def +/Bc /Bm load def +/Bh {4 npop} def +end +/Lb +{ + 6 npop + 7 2 roll + 5 npop + 0 eq + { + 0 eq + { + (%AI5_BeginLayer) 1 (%AI5_EndLayer--) discard + } + { + + /clipForward? true def + + /Tx /pop load def + /Tj /pop load def + + currentdict end clipRenderOff begin begin + } ifelse + } + { + 0 eq + { + save /discardSave exch store + } if + } ifelse +} bind def +/LB +{ + discardSave dup null ne + { + restore + } + { + pop + clipForward? + { + currentdict + end + end + begin + + /clipForward? false ddef + } if + } ifelse +} bind def +/Pb +{ + pop pop + 0 (%AI5_EndPalette) discard +} bind def +/Np +{ + 0 (%AI5_End_NonPrinting--) discard +} bind def +/Ln /pop load def +/Ap +/pop load def +/Ar +{ + 72 exch div + 0 dtransform dup mul exch dup mul add sqrt + dup 1 lt + { + pop 1 + } if + setflat +} def +/Mb +{ + q +} def +/Md +{ +} def +/MB +{ + Q +} def +/nc 4 dict def +nc begin +/setgray +{ + pop +} bind def +/setcmykcolor +{ + 4 npop +} bind def +/setrgbcolor +{ + 3 npop +} bind def +/setcustomcolor +{ + 2 npop +} bind def +currentdict readonly pop +end +/XP +{ + 4 npop +} bind def +/XD +{ + pop +} bind def +end +setpacking +%%EndResource +%%BeginResource: procset Adobe_cshow 2.0 8 +%%Title: (Writing System Operators) +%%Version: 2.0 8 +%%CreationDate: (1/23/89) () +%%Copyright: ((C) 1992-1996 Adobe Systems Incorporated All Rights Reserved) +currentpacking true setpacking +userdict /Adobe_cshow 14 dict dup begin put +/initialize +{ + Adobe_cshow begin + Adobe_cshow + { + dup xcheck + { + bind + } if + pop pop + } forall + end + Adobe_cshow begin +} def +/terminate +{ +currentdict Adobe_cshow eq + { + end + } if +} def +/cforall +{ + /_lobyte 0 ddef + /_hibyte 0 ddef + /_cproc exch ddef + /_cscript currentfont /FontScript known { currentfont /FontScript get } { -1 } ifelse ddef + { + /_lobyte exch ddef + _hibyte 0 eq + _cscript 1 eq + _lobyte 129 ge _lobyte 159 le and + _lobyte 224 ge _lobyte 252 le and or and + _cscript 2 eq + _lobyte 161 ge _lobyte 254 le and and + _cscript 3 eq + _lobyte 161 ge _lobyte 254 le and and + _cscript 25 eq + _lobyte 161 ge _lobyte 254 le and and + _cscript -1 eq + or or or or and + { + /_hibyte _lobyte ddef + } + { + _hibyte 256 mul _lobyte add + _cproc + /_hibyte 0 ddef + } ifelse + } forall +} def +/cstring +{ + dup 256 lt + { + (s) dup 0 4 3 roll put + } + { + dup 256 idiv exch 256 mod + (hl) dup dup 0 6 5 roll put 1 4 3 roll put + } ifelse +} def +/clength +{ + 0 exch + { 256 lt { 1 } { 2 } ifelse add } cforall +} def +/hawidthshow +{ + { + dup cstring + show + _hvax _hvay rmoveto + _hvwb eq { _hvcx _hvcy rmoveto } if + } cforall +} def +/vawidthshow +{ + { + dup 255 le + _charorientation 1 eq + and + { + -90 rotate + 0 _fontRotateAdjust rmoveto + cstring + _hvcx _hvcy _hvwb _hvax _hvay 6 -1 roll awidthshow + 0 _fontRotateAdjust neg rmoveto + 90 rotate + } + { + currentpoint + _fontHeight sub + exch _hvay sub exch _hvax sub + 2 index _hvwb eq { exch _hvcy sub exch _hvcx sub } if + 3 2 roll + cstring + dup stringwidth pop 2 div neg _fontAscent neg rmoveto + show + moveto + } ifelse + } cforall +} def +/hvawidthshow +{ + 6 1 roll + /_hvay exch ddef + /_hvax exch ddef + /_hvwb exch ddef + /_hvcy exch ddef + /_hvcx exch ddef + _lineorientation 0 eq { hawidthshow } { vawidthshow } ifelse +} def +/hvwidthshow +{ + 0 0 3 -1 roll hvawidthshow +} def +/hvashow +{ + 0 0 0 6 -3 roll hvawidthshow +} def +/hvshow +{ + 0 0 0 0 0 6 -1 roll hvawidthshow +} def +currentdict readonly pop end +setpacking +%%EndResource +%%BeginResource: procset Adobe_shading_AI8 1.0 0 +%%Title: (Adobe Illustrator 8 Shading Procset) +%%Version: 1.0 0 +%%CreationDate: (12/17/97) () +%%Copyright: ((C) 1987-1997 Adobe Systems Incorporated All Rights Reserved) +userdict /defaultpacking currentpacking put true setpacking +userdict /Adobe_shading_AI8 10 dict dup begin put +/initialize { + Adobe_shading_AI8 begin + Adobe_shading_AI8 bdprocs + Mesh /initialize get exec +} def +/terminate { + currentdict Adobe_shading_AI8 eq { + end + } if +} def +/bdprocs { + { + dup xcheck 1 index type /arraytype eq and { + bind + } if + pop pop + } forall +} def +/X! {pop} def +/X# {pop pop} def +/Mesh 40 dict def +Mesh begin +/initialize { + Mesh bdprocs + Mesh begin + /emulate? /AI8MeshEmulation where { + pop AI8MeshEmulation + }{ + systemdict /shfill known not + } ifelse def + end +} def +/bd { + shadingdict begin +} def +/paint { + emulate? { + end + }{ + /_lp /none ddef _fc /_lp /none ddef + + /AIColorSpace AIColorSpace tocolorspace store + /ColorSpace AIColorSpace topsspace store + + version_ge_3010.106 not systemdict /setsmoothness known and { + 0.0001 setsmoothness + } if + + composite? { + /DataSource getdatasrc def + Matrix concat + currentdict end + shfill + }{ + AIColorSpace makesmarks AIPlateList markingplate and not isoverprint and { + end + }{ + /ColorSpace /DeviceGray store + /Decode [0 1 0 1 0 1] store + /DataSource getplatesrc def + Matrix concat + currentdict end + shfill + } ifelse + } ifelse + } ifelse +} def +/shadingdict 12 dict def +shadingdict begin + /ShadingType 6 def + /BitsPerCoordinate 16 def + /BitsPerComponent 8 def + /BitsPerFlag 8 def +end +/datafile null def +/databuf 256 string def +/dataptr 0 def +/srcspace null def +/srcchannels 0 def +/dstchannels 0 def +/dstplate 0 def +/srctodstcolor null def +/getplatesrc { + /srcspace AIColorSpace store + /srcchannels AIColorSpace getnchannels store + /dstchannels 1 store + /dstplate getplateindex store + /srctodstcolor srcspace makesmarks { + dstplate 4 eq { + {1 exch sub} + }{ + {srcspace tocmyk 3 dstplate sub index 1 exch sub 5 1 roll 4 {pop} repeat} + } ifelse + }{ + {srcchannels {pop} repeat 1} + } ifelse store + /datafile getdatasrc store + /rdpatch168 load DataLength () /SubFileDecode filter +} def +/getdatasrc { + /rdcmntline load /ASCII85Decode filter +} def +/rdpatch168 { + /dataptr 0 store + 49 rdcount + 4 { + dup {pop srcchannels getint8} if + dup {pop srctodstcolor dstchannels putint8 true} if + } repeat + {databuf 0 dataptr getinterval}{()} ifelse +} def +/rdpatch3216 { + /dataptr 0 store + 97 rdcount + 4 { + dup {pop srcchannels getint16} if + dup {pop srctodstcolor dstchannels putint16 true} if + } repeat + {databuf 0 dataptr getinterval}{()} ifelse +} def +/rdcount { + dup 0 gt { + datafile databuf dataptr 4 -1 roll getinterval readstring + exch length dataptr add /dataptr exch store + }{ + true + } ifelse +} def +/getint8 { + mark true 3 -1 roll + { + dup {pop datafile read} if + dup {pop 255 div true} if + } repeat + { + counttomark 1 add -1 roll pop true + }{ + cleartomark false + } ifelse +} def +/putint8 { + dup dataptr add /dataptr exch store + dataptr exch + { + 1 sub exch + 255 mul cvi + databuf 2 index + 3 -1 roll put + } repeat + pop +} def +/getint16 { + mark true 3 -1 roll + { + dup {pop datafile read} if + dup {pop 256 mul datafile read} if + dup {pop add 65535 div true} if + } repeat + { + counttomark 1 add -1 roll pop true + }{ + cleartomark false + } ifelse +} def +/putint16 { + dup 2 mul dataptr add /dataptr exch store + dataptr exch + { + 2 sub exch + 65535 mul cvi dup + 256 idiv databuf 3 index 3 -1 roll put + 256 mod databuf 2 index 1 add 3 -1 roll put + } repeat + pop +} def +/srcbuf 256 string def +/rdcmntline { + currentfile srcbuf readline pop + (%) anchorsearch {pop} if +} def +/getplateindex { + 0 [cyan? magenta? yellow? black? customColor?] {{exit} if 1 add} forall +} def +/aicsarray 4 array def +/aicsaltvals 4 array def +/aicsaltcolr aicsaltvals def +/tocolorspace { + dup type /arraytype eq { + mark exch aload pop + aicsarray 0 3 -1 roll put + aicsarray 1 3 -1 roll put + dup aicsarray 2 3 -1 roll put + gettintxform aicsarray 3 3 -1 roll put + counttomark aicsaltvals 0 3 -1 roll getinterval /aicsaltcolr exch store + aicsaltcolr astore pop pop + aicsarray + } if +} def +/subtintxform {aicsaltcolr {1 index mul exch} forall pop} def +/addtintxform {aicsaltcolr {1 sub 1 index mul 1 add exch} forall pop} def +/gettintxform { + /DeviceRGB eq {/addtintxform}{/subtintxform} ifelse load +} def +/getnchannels { + dup type /arraytype eq {0 get} if + colorspacedict exch get begin Channels end +} def +/makesmarks { + composite? { + pop true + }{ + dup dup type /arraytype eq {0 get} if + colorspacedict exch get begin MarksPlate end + } ifelse +} def +/markingplate { + composite? { + pop true + }{ + dup type /arraytype eq { + dup length getplateindex gt {getplateindex get}{pop false} ifelse + } if + } ifelse +} def +/tocmyk { + dup dup type /arraytype eq {0 get} if + colorspacedict exch get begin ToCMYK end +} def +/topsspace { + dup dup type /arraytype eq {0 get} if + colorspacedict exch get begin ToPSSpace end +} def +/colorspacedict 5 dict dup begin + /DeviceGray 4 dict dup begin + /Channels 1 def + /MarksPlate {pop black?} def + /ToCMYK {pop 1 exch sub 0 0 0 4 -1 roll} def + /ToPSSpace {} def + end def + /DeviceRGB 4 dict dup begin + /Channels 3 def + /MarksPlate {pop isCMYKSep?} def + /ToCMYK {pop _rgbtocmyk} def + /ToPSSpace {} def + end def + /DeviceCMYK 4 dict dup begin + /Channels 4 def + /MarksPlate {pop isCMYKSep?} def + /ToCMYK {pop} def + /ToPSSpace {} def + end def + /Separation 4 dict dup begin + /Channels 1 def + /MarksPlate { + /findcmykcustomcolor where { + pop dup 1 exch ToCMYK 5 -1 roll 1 get + findcmykcustomcolor 1 setcustomcolor + systemdict /currentgray get exec + 1 ne + }{ + pop false + } ifelse + } def + /ToCMYK { + dup 2 get mark exch 4 2 roll + 3 get exec + counttomark -1 roll tocmyk + 5 -1 roll pop + } def + /ToPSSpace {} def + end def + /Process 4 dict dup begin + /Channels 1 def + /MarksPlate { + isCMYKSep? { + 1 exch ToCMYK 4 array astore getplateindex get 0 ne + }{ + pop false + } ifelse + } def + /ToCMYK { + dup 2 get mark exch 4 2 roll + 3 get exec + counttomark -1 roll tocmyk + 5 -1 roll pop + } def + /ToPSSpace { + 4 array copy dup 0 /Separation put + } def + end def +end def +/isoverprint { + /currentoverprint where {pop currentoverprint}{_of} ifelse +} def +/version_ge_3010.106 { + version {cvr} stopped { + pop + false + }{ + 3010.106 ge + } ifelse +} def +end +end +defaultpacking setpacking +%%EndResource +%%EndProlog
%%BeginSetup
userdict /_useSmoothShade false put
userdict /_aicmykps true put
userdict /_forceToCMYK true put
Adobe_level2_AI5 /initialize get exec +Adobe_cshow /initialize get exec +Adobe_ColorImage_AI6 /initialize get exec +Adobe_shading_AI8 /initialize get exec +Adobe_Illustrator_AI5 /initialize get exec +%AI3_BeginRider
currentpacking true setpacking
setpacking
%AI3_EndRider
%AI5_Begin_NonPrinting
Np
%AI8_PluginGroupInfo
(Adobe Path Blends) (Adobe Blends Plugin) (LiveBlends.aip)
%AI8_PluginGroupInfo
(Adobe Tracing Object) (Tracing) (TracingSuite.aip)
%AI8_PluginGroupInfo
(Adobe Scatter Brush Tool) (Adobe Scatter Brush Plugin) (ScatterBrushTool.aip)
%AI8_PluginGroupInfo
(Adobe Scatter Brush Tool) (Adobe Scatter Brush Plugin) (ScatterBrushTool.aip)
%AI8_PluginGroupInfo
(Adobe PatternOnPath Brush Tool) (Adobe Pattern Brush Plugin) (ArtBrushTool.aip)
%AI8_PluginGroupInfo
(Adobe PatternOnPath Brush Tool) (Adobe Pattern Brush Plugin) (ArtBrushTool.aip)
%AI8_PluginGroupInfo
(Adobe ArtOnPath Brush Tool) (Adobe Art Brush Plugin) (ArtBrushTool.aip)
%AI8_PluginGroupInfo
(Adobe ArtOnPath Brush Tool) (Adobe Art Brush Plugin) (ArtBrushTool.aip)
%AI8_PluginGroupInfo
(Adobe Calligraphic Brush Tool) (Adobe Calligraphic Brush Plugin) (CalligBrushTool.aip)
%AI8_PluginGroupInfo
(Adobe Flare Plugin) (Flare) (Flare.aip)
%AI8_PluginGroupInfo
(Adobe Symbolism) (Adobe Symbolism) (ParticleSystem.aip)
%AI8_PluginGroupInfo
(Adobe Deform Plugin) (Adobe Envelope Plugin) (Envelope and Warp.aip)
%AI8_PluginGroupInfo
(Pathfinder Suite) (Adobe Compound Shape) (PathFinderS.aip)
%AI8_PluginGroupInfo
(Adobe Planar Group) (Adobe Live Paint Plugin) (Live Paint.aip)
%AI5_End_NonPrinting--
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%AI5_EndPalette
%%EndSetup
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%AI5_EndLayer--
%AI3_BeginCrops
userdict /AI3_noCropMarks known not {
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u
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S
U
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} if
%AI3_EndCrops
%%PageTrailer
gsave annotatepage grestore showpage
%%Trailer
Adobe_Illustrator_AI5 /terminate get exec +Adobe_shading_AI8 /terminate get exec +Adobe_ColorImage_AI6 /terminate get exec +Adobe_cshow /terminate get exec +Adobe_level2_AI5 /terminate get exec +%%EOF
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