diff options
| -rw-r--r-- | plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c index 0af591c5d..fc84ba439 100644 --- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c @@ -138,7 +138,6 @@ static struct bl31_configs { #define RDC_CFG_ITEMS (12-5) static struct imx_rdc_cfg g_rdc_cfg[RDC_CFG_ITEMS]; -#if 0 static const struct imx_rdc_cfg g_rdc_cfg_mda[] = { /* Master domain assignment */ RDC_MDAn(RDC_MDA_A53, DID0 | LCK), @@ -148,11 +147,10 @@ static const struct imx_rdc_cfg g_rdc_cfg_mda[] = { RDC_MDAn(RDC_MDA_DCSS, DID3| LCK), { 0 } }; -#endif + static void setup_rdc_configs(void) { int index = 0; - /* peripherals domain permission */ /* memory region */ /* @@ -242,12 +240,21 @@ static void setup_rdc_configs(void) /* Sentinel */ memset(&g_rdc_cfg[index], 0, sizeof g_rdc_cfg[index]); + + INFO("dcss_buf_base/leng= 0x%08x/%08x, decode_buf_base/leng= 0x%08x/%08x, decrypt_buf_base/leng=0x%08x/%08x.\n", + gp_configs->dcss_buf_base, gp_configs->dcss_buf_leng, + gp_configs->decode_buf_base, gp_configs->decode_buf_leng, + gp_configs->decrypt_buf_base, gp_configs->decrypt_buf_leng); } #endif /* RDC_ENABLED */ static const struct imx_csu_cfg csu_cfg_conf[] = { /* peripherals csl setting */ #ifdef CFG_SECURE_HANTRO_VPU + /* + * VPU as slave peripheral to A53's access permission. + * CSU_SEC_LEVEL_5 -> Secure state/Priv mode + */ CSU_CSLx(CSU_CSL_VPU_SEC, CSU_SEC_LEVEL_5, LOCKED), #endif #ifdef DRM_SDP_HDCP_TA @@ -271,10 +278,8 @@ static void bl31_imx_rdc_setup(void) ERROR("RDC off \n"); #else setup_rdc_configs(); -#if 0 imx_rdc_init(g_rdc_cfg_mda); imx_rdc_init(g_rdc_cfg); -#endif #endif // RDC_DISABLED } @@ -317,7 +322,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, { int i; - /* enable CSU NS access permission */ + /* enable A53 NS/S(user/priv modes) access permission to all slave peripherals??? */ for (i = 0; i < 64; i++) { mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff); } @@ -355,15 +360,23 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, * bl31_image_entry(X0, X1, ...). SPL will use arg1 to pass bl31_configs' * address into BL31. * If arg1 is NULL, means no OP-TEE & bl31_configs were detected by SPL. + * + * Pass TEE base and size to bl33. In case no BL2-FIT is detected, + * we pass "0" size over to U-Boot and these parameters will pass via + * CPU regsiters, Check UBoot's rom_pointer global variables. */ gp_configs = (struct bl31_configs *)arg1; - bl32_image_ep_info.pc = (!gp_configs || !gp_configs->tee_presence)? 0 : BL32_BASE; + if (!gp_configs || !gp_configs->tee_presence) { + bl32_image_ep_info.pc = 0; + bl33_image_ep_info.args.arg1 = 0; + bl33_image_ep_info.args.arg2 = 0; + } else { + bl32_image_ep_info.pc = BL32_BASE; + bl33_image_ep_info.args.arg1 = BL32_BASE; + bl33_image_ep_info.args.arg2 = BL32_SIZE; + } bl32_image_ep_info.spsr = 0; - /* Pass TEE base and size to bl33 */ - bl33_image_ep_info.args.arg1 = BL32_BASE; - bl33_image_ep_info.args.arg2 = BL32_SIZE; - #ifdef SPD_trusty bl32_image_ep_info.args.arg0 = BL32_SIZE; bl32_image_ep_info.args.arg1 = BL32_BASE; @@ -387,7 +400,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, #endif bl31_imx_rdc_setup(); - } void bl31_plat_arch_setup(void) |