diff options
| -rw-r--r-- | core/arch/arm/kernel/stmm_sp.c | 73 | ||||
| -rw-r--r-- | core/arch/arm/mm/core_mmu_lpae.c | 3 | ||||
| -rw-r--r-- | core/arch/arm/mm/mobj.c | 19 | ||||
| -rw-r--r-- | core/arch/arm/plat-vexpress/conf.mk | 1 |
4 files changed, 86 insertions, 10 deletions
diff --git a/core/arch/arm/kernel/stmm_sp.c b/core/arch/arm/kernel/stmm_sp.c index f701c1a6..7fff3932 100644 --- a/core/arch/arm/kernel/stmm_sp.c +++ b/core/arch/arm/kernel/stmm_sp.c @@ -82,12 +82,14 @@ static TEE_Result alloc_SPD_io(struct stmm_ctx *spc, paddr_t pa, struct mobj *mobj; TEE_Result res = TEE_SUCCESS; *va = 0x0; - sz = ROUNDUP(sz, SMALL_PAGE_SIZE); - mobj = mobj_phys_alloc(pa, sz, 0, CORE_MEM_SDP_MEM); + mobj = mobj_phys_alloc(pa, sz, TEE_MATTR_CACHE_NONCACHE, CORE_MEM_SDP_MEM); - if (!mobj) + if (!mobj) { + EMSG("out of memory when allocating mobj\n"); return TEE_ERROR_OUT_OF_MEMORY; + } + res = vm_map_pad(&spc->uctx, va, sz, prot, 0, mobj, @@ -105,7 +107,62 @@ static TEE_Result hack_map_StMM_devices(struct stmm_ctx *spc) { TEE_Result res; vaddr_t uart_va = 0; - res = alloc_SPD_io(spc, 0x09040000, 0x00001000, +#if defined(CFG_MX8MM) +EMSG("hack alloc device regions\n"); + // imx8mm-evk UART + res = alloc_SPD_io(spc, 0x30890000, 0x00001000, + TEE_MATTR_URW | TEE_MATTR_PRW, + &uart_va, 0, 0); + if (res) { + EMSG("failed to alloc_and_map uart"); + return res; + } + EMSG("------------------------------uart va=%#"PRIxVA, uart_va); + +/* + res = alloc_SPD_io(spc, 0xe05f000, 0x1000, + TEE_MATTR_URW | TEE_MATTR_PRW, + &uart_va, 0, 0); + if (res) { + EMSG("failed to alloc_and_map secure flash"); + return res; + } + EMSG("------------------------------secure FWU page (SRAM) va=%#"PRIxVA, uart_va); +*/ + + // imx8mm-evk QSPI controller + res = alloc_SPD_io(spc, 0x30bb0000, 0x1000, + TEE_MATTR_URW | TEE_MATTR_PRW, + &uart_va, 0, 0); + if (res) { + EMSG("failed to alloc_and_map secure flash"); + return res; + } + EMSG("------------------------------FlexSPI controller va=%#"PRIxVA, uart_va); + + + // imx8mm-evk CCM_CCGR (MMIO region that controlls clocks) + res = alloc_SPD_io(spc, 0x30380000, 0xB000, + TEE_MATTR_URW | TEE_MATTR_PRW, + &uart_va, 0, 0); + if (res) { + EMSG("failed to alloc_and_map CCM_CCGR"); + return res; + } + EMSG("------------------------------CCM_CCGR controller va=%#"PRIxVA, uart_va); + + // imx8mm-evk IOMUX PAD + res = alloc_SPD_io(spc, 0x30330000, 0x1000, + TEE_MATTR_URW | TEE_MATTR_PRW, + &uart_va, 0, 0); + if (res) { + EMSG("failed to alloc_and_map IOMUX PAD"); + return res; + } + EMSG("------------------------------IOMUX PAD va=%#"PRIxVA, uart_va); +#elif defined(CFG_QEMUVIRT) + //res = alloc_SPD_io(spc, 0x09040000, 0x00001000, + res = alloc_SPD_io(spc, 0x09000000, 0x00001000, TEE_MATTR_URW | TEE_MATTR_PRW, &uart_va, 0, 0); if (res) { @@ -116,7 +173,8 @@ static TEE_Result hack_map_StMM_devices(struct stmm_ctx *spc) // Secure variable storage // base address at from [0x0, 0xA00000[ - res = alloc_SPD_io(spc, 0x000000, 0xA00000, + //res = alloc_SPD_io(spc, 0x000000, 0xA00000, + res = alloc_SPD_io(spc, 0x000000, 0x700000, TEE_MATTR_URW | TEE_MATTR_PRW, &uart_va, 0, 0); if (res) { @@ -134,6 +192,11 @@ static TEE_Result hack_map_StMM_devices(struct stmm_ctx *spc) } EMSG("------------------------------secure FWU page (SRAM) va=%#"PRIxVA, uart_va); + +#else +#error "Unsupported platform" +#endif + return res; } static struct stmm_ctx *stmm_alloc_ctx(const TEE_UUID *uuid) diff --git a/core/arch/arm/mm/core_mmu_lpae.c b/core/arch/arm/mm/core_mmu_lpae.c index ed753105..81749f32 100644 --- a/core/arch/arm/mm/core_mmu_lpae.c +++ b/core/arch/arm/mm/core_mmu_lpae.c @@ -771,7 +771,8 @@ void core_mmu_set_entry_primitive(void *table, size_t level, size_t idx, { uint64_t *tbl = table; uint64_t desc = mattr_to_desc(level, attr); - +// if (pa<0xbe000000) +// EMSG(" pa=%x ", pa); tbl[idx] = desc | pa; } diff --git a/core/arch/arm/mm/mobj.c b/core/arch/arm/mm/mobj.c index 7a129cf5..7d8e19d8 100644 --- a/core/arch/arm/mm/mobj.c +++ b/core/arch/arm/mm/mobj.c @@ -147,13 +147,21 @@ struct mobj *mobj_phys_alloc(paddr_t pa, size_t size, uint32_t cattr, area_type = MEM_AREA_TEE_RAM_RW_DATA; break; case CORE_MEM_TA_RAM: - area_type = MEM_AREA_TA_RAM; + if (cattr==TEE_MATTR_CACHE_NONCACHE) + area_type = MEM_AREA_IO_NSEC; + else + area_type = MEM_AREA_TA_RAM; + break; case CORE_MEM_NSEC_SHM: area_type = MEM_AREA_NSEC_SHM; break; case CORE_MEM_SDP_MEM: - area_type = MEM_AREA_SDP_MEM; + if (cattr==TEE_MATTR_CACHE_NONCACHE) + area_type = MEM_AREA_IO_NSEC; + else + area_type = MEM_AREA_SDP_MEM; + break; default: DMSG("can't allocate with specified attribute"); @@ -161,8 +169,11 @@ struct mobj *mobj_phys_alloc(paddr_t pa, size_t size, uint32_t cattr, } /* Only SDP memory may not have a virtual address */ - va = phys_to_virt(pa, area_type); - if (!va && battr != CORE_MEM_SDP_MEM) + if (area_type == MEM_AREA_IO_SEC || area_type == MEM_AREA_IO_NSEC) + va = phys_to_virt_io(pa); + else + va = phys_to_virt(pa, area_type); + if (!va && battr != CORE_MEM_SDP_MEM) return NULL; moph = calloc(1, sizeof(*moph)); diff --git a/core/arch/arm/plat-vexpress/conf.mk b/core/arch/arm/plat-vexpress/conf.mk index 26b9f51e..02310f13 100644 --- a/core/arch/arm/plat-vexpress/conf.mk +++ b/core/arch/arm/plat-vexpress/conf.mk @@ -22,6 +22,7 @@ endif endif #juno ifeq ($(PLATFORM_FLAVOR),qemu_armv8a) include core/arch/arm/cpu/cortex-armv8-0.mk +$(call force,CFG_QEMUVIRT, y) CFG_ARM64_core ?= y endif |