diff options
| author | etienne carriere <etienne.carriere@st.com> | 2014-12-02 15:44:25 +0100 |
|---|---|---|
| committer | Pascal Brand <pascal.brand@st.com> | 2015-01-30 14:53:48 +0100 |
| commit | a9985f3daefe46a6138e0e9a8016294a3dc81562 (patch) | |
| tree | 3b43d009c6f5bbb6ad117831a80b7c89c04ae933 /core | |
| parent | c643dd49f5ae7b98f8d0a32beb3372d3740a1295 (diff) | |
core/arm32: support PL310 lockdown at TEE boot
Add routine arm_cl2_lockgit allways() that enable lock on all d/i ways.
Add config switch CFG_PL310_LOCKED. If set, at TEE boot, PL310 L2 cache
is fully locked and invalidated. Once TZ as booted, NSec inherits from
a pre-configured L2 cache, pre-enable, but bypassed as all ways are
locked. If NSec wants to benefit from L2 cache, it shall unlock all
d/i ways.
Default setup: CFG_PL310_LOCKED is not defined. Linux may not integrate
the outercache unlock sequence at l2x0 inits.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Reviewed-on: https://gerrit.st.com/17088
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/arch/arm32/include/kernel/tz_ssvce_def.h | 4 | ||||
| -rw-r--r-- | core/arch/arm32/kernel/tz_ssvce_pl310.S | 16 | ||||
| -rw-r--r-- | core/arch/arm32/plat-stm/system_config.in | 3 | ||||
| -rw-r--r-- | core/arch/arm32/plat-stm/tz_sinit.S | 7 |
4 files changed, 28 insertions, 2 deletions
diff --git a/core/arch/arm32/include/kernel/tz_ssvce_def.h b/core/arch/arm32/include/kernel/tz_ssvce_def.h index d66cf26..9937899 100644 --- a/core/arch/arm32/include/kernel/tz_ssvce_def.h +++ b/core/arch/arm32/include/kernel/tz_ssvce_def.h @@ -75,6 +75,7 @@ * Outer cache iomem */ #define PL310_LINE_SIZE 32 +#define PL310_NB_WAYS 8 #define PL310_BASE_H ((PL310_BASE >> 16) & 0xFFFF) #define PL310_BASE_L (PL310_BASE & 0xFFFF) @@ -92,6 +93,9 @@ #define PL310_CLEAN_BY_PA (PL310_BASE_L | 0x7B0) #define PL310_FLUSH_BY_PA (PL310_BASE_L | 0x7F0) #define PL310_FLUSH_BY_INDEXWAY (PL310_BASE_L | 0x7F8) +/* reg9 */ +#define PL310_DCACHE_LOCKDOWN_BASE (PL310_BASE_L | 0x900) +#define PL310_ICACHE_LOCKDOWN_BASE (PL310_BASE_L | 0x904) /* reg12 */ #define PL310_ADDR_FILT_START (PL310_BASE_L | 0xC00) #define PL310_ADDR_FILT_END (PL310_BASE_L | 0xC04) diff --git a/core/arch/arm32/kernel/tz_ssvce_pl310.S b/core/arch/arm32/kernel/tz_ssvce_pl310.S index d0b3b01..874af4d 100644 --- a/core/arch/arm32/kernel/tz_ssvce_pl310.S +++ b/core/arch/arm32/kernel/tz_ssvce_pl310.S @@ -29,6 +29,7 @@ #include <kernel/tz_ssvce_def.h> /* cache maintenance */ +.global arm_cl2_lockallways .global arm_cl2_cleaninvbyway .global arm_cl2_invbyway .global arm_cl2_cleanbyway @@ -36,6 +37,21 @@ .global arm_cl2_invbypa .global arm_cl2_cleaninvbypa +/* lock all L2 caches ways for data and instruction */ +arm_cl2_lockallways: + + mov r0, #PL310_NB_WAYS + movw r1, #PL310_DCACHE_LOCKDOWN_BASE + movt r1, #PL310_BASE_H + movw r2, #0xFFFF /* LD ways constant */ +loop_data_lockdown: + str r2, [r1], #0x04 /* lock way for Dcache */ + str r2, [r1], #0x04 /* lock way for Icache */ + subs r0, r0, #1 + bne loop_data_lockdown + + mov pc, lr + /* * void arm_cl2_cleaninvbyway(void) - clean & invalidate the whole L2 cache. */ diff --git a/core/arch/arm32/plat-stm/system_config.in b/core/arch/arm32/plat-stm/system_config.in index 1810a67..192e3f6 100644 --- a/core/arch/arm32/plat-stm/system_config.in +++ b/core/arch/arm32/plat-stm/system_config.in @@ -40,3 +40,6 @@ endif # Common values CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= 1 + +# undef these to disable the related feature +CFG_PL310_LOCKED ?= n diff --git a/core/arch/arm32/plat-stm/tz_sinit.S b/core/arch/arm32/plat-stm/tz_sinit.S index df183d6..4df7356 100644 --- a/core/arch/arm32/plat-stm/tz_sinit.S +++ b/core/arch/arm32/plat-stm/tz_sinit.S @@ -228,8 +228,6 @@ init_bss: /* Flush all caches before secondary CPUs setup */ bl arm_cl1_d_cleaninvbysetway bl arm_cl2_cleaninvbyway - bl arm_cl1_d_cleaninvbysetway - sev /* Primary CPU waits secondary */ @@ -241,6 +239,11 @@ _wait_cpu1: wfene bne _wait_cpu1 +#ifdef CFG_PL310_LOCKED + bl arm_cl2_lockallways + bl arm_cl2_invbyway +#endif + /* TODO: call teecore inits */ /* ask monitor to enter NSec from TEE boot sequence */ |