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/*
* Copyright (c) 2012, ARM Limited. All rights reserved.
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimer.
*
* Redistributions in binary form must reproduce the
* above copyright notice, this list of conditions and
* the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its
* contributors may be used to endorse or promote products
* derived from this software without specific prior written
* permission.
*/
#include "scf-macros.h"
#ifdef BUILD_RVCT
VECTORS PASTE(VECTBASE,00000) 0x100
{
VECTORSEXEC PASTE(VECTBASE,00000) 0x100
{
vectors.o (+RO,+RW,+ZI)
}
}
KERNELBA KERNADDRBA 0x4000
{
KERNELBA KERNADDRBA 0x4000
{
bootargs.o (+RO,+RW,+ZI)
}
}
KERNEL KERNADDR 0x800000
{
KERNEL KERNADDR 0x800000
{
kernel.o (kernel)
}
}
FILESYSTEM FSADDR 0x2000000
{
FILESYSTEM FSADDR 0x2000000
{
filesystem.o (filesystem)
}
}
/*
* BIOS code is placed in the last 128kB of RAM
* Linux can just be told to use 0-HIBASEMB
*/
HIGHCODE PASTE(HIBASE,E0000) 0x00018000
{
HIGHCODEALL +0
{
*.o (*)
}
}
/* Include generated load map info for payload binaries: */
#include "bl.embed.scf"
#include "bl_sec.embed.scf"
#else /* ! BUILD_RVCT */
SECTIONS {
/*
* Include generated load map info for payload binaries:
* These must go first so that wildcards don't pull these into other sections.
*/
#include "bl.embed.scf"
#include "bl_sec.embed.scf"
VECTORS PASTE(VECTBASE,00000) : {
vectors.o(.text .text.*)
}
KERNELBA KERNADDRBA : {
bootargs.o(.data .data.*)
}
KERNEL KERNADDR : {
kernel.o(.rodata .rodata.*)
}
FILESYSTEM FSADDR : {
filesystem.o(.rodata .rodata.*)
}
/*
* BIOS code is placed in the last 128kB of RAM
* Linux can just be told to use 0-HIBASEMB
*/
HIGHCODE PASTE(HIBASE,E0000) : {
*(.text .text.*)
*(.rodata .rodata.*)
}
HIGHDATA : {
*(.data .data.*)
*(COMMON)
*(.bss .bss.*)
}
/* Include debug information sections: */
.debug_line 0 : { *(.debug_line) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_ranges 0 : { *(.debug_ranges) }
.debug_str 0 : { *(.debug_str) }
/DISCARD/ : {
*(*)
}
}
#endif /* ! BUILD_RVCT */
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