diff options
| author | Loh Tien Hock <tien.hock.loh@intel.com> | 2019-02-04 16:17:24 +0800 |
|---|---|---|
| committer | Loh Tien Hock <tien.hock.loh@intel.com> | 2019-02-04 16:17:24 +0800 |
| commit | 9d82ef26c657fda9ee21806817c7a16547b0b605 (patch) | |
| tree | 37e91b6220d389baf4276e9c0ea05fea10c284f4 /maintainers.rst | |
| parent | f0bfe15b81e50c6561a3a9a8e269db0267778910 (diff) | |
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Diffstat (limited to 'maintainers.rst')
| -rw-r--r-- | maintainers.rst | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/maintainers.rst b/maintainers.rst index f53dda52..1f7d03e7 100644 --- a/maintainers.rst +++ b/maintainers.rst @@ -93,6 +93,12 @@ HiSilicon Poplar platform port :F: docs/plat/poplar.rst :F: plat/hisilicon/poplar/ +Intel SocFPGA platform ports +---------------------------- +:M: Tien Hock Loh <tien.hock.loh@intel.com> +:G: `thloh85-intel` +:F: plat/intel/soc + MediaTek platform ports ----------------------- :M: Yidi Lin (林以廸) <yidi.lin@mediatek.com> |