Merge pull request #1845 from ambroise-arm/av/errata

Apply workarounds for errata of Cortex-A53, A55 and A57

6 files changed, 488 insertions, 5 deletions

diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index 4975ec60..6e3ff817 100644
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -29,6 +29,36 @@ func cortex_a53_disable_smp
 	bx	lr
 endfunc cortex_a53_disable_smp
 
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A53 Errata #819472.
+	 * This applies only to revision <= r0p1 of Cortex A53.
+	 * ---------------------------------------------------
+	 */
+func check_errata_819472
+	/*
+	 * Even though this is only needed for revision <= r0p1, it
+	 * is always applied due to limitations of the current
+	 * errata framework.
+	 */
+	mov	r0, #ERRATA_APPLIES
+	bx	lr
+endfunc check_errata_819472
+
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A53 Errata #824069.
+	 * This applies only to revision <= r0p2 of Cortex A53.
+	 * ---------------------------------------------------
+	 */
+func check_errata_824069
+	/*
+	 * Even though this is only needed for revision <= r0p2, it
+	 * is always applied due to limitations of the current
+	 * errata framework.
+	 */
+	mov	r0, #ERRATA_APPLIES
+	bx	lr
+endfunc check_errata_824069
+
 	/* --------------------------------------------------
 	 * Errata Workaround for Cortex A53 Errata #826319.
 	 * This applies only to revision <= r0p2 of Cortex A53.
@@ -59,6 +89,21 @@ func check_errata_826319
 	b	cpu_rev_var_ls
 endfunc check_errata_826319
 
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A53 Errata #827319.
+	 * This applies only to revision <= r0p2 of Cortex A53.
+	 * ---------------------------------------------------
+	 */
+func check_errata_827319
+	/*
+	 * Even though this is only needed for revision <= r0p2, it
+	 * is always applied due to limitations of the current
+	 * errata framework.
+	 */
+	mov	r0, #ERRATA_APPLIES
+	bx	lr
+endfunc check_errata_827319
+
 	/* ---------------------------------------------------------------------
 	 * Disable the cache non-temporal hint.
 	 *
@@ -253,7 +298,10 @@ func cortex_a53_errata_report
 	 * Report all errata. The revision-variant information is passed to
 	 * checking functions of each errata.
 	 */
+	report_errata ERRATA_A53_819472, cortex_a53, 819472
+	report_errata ERRATA_A53_824069, cortex_a53, 824069
 	report_errata ERRATA_A53_826319, cortex_a53, 826319
+	report_errata ERRATA_A53_827319, cortex_a53, 827319
 	report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
 	report_errata ERRATA_A53_855873, cortex_a53, 855873
 
diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S
index 04942d30..2e97abbe 100644
--- a/lib/cpus/aarch32/cortex_a57.S
+++ b/lib/cpus/aarch32/cortex_a57.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -46,6 +46,13 @@ func cortex_a57_disable_ext_debug
 	mov	r0, #1
 	stcopr	r0, DBGOSDLR
 	isb
+#if ERRATA_A57_817169
+	/*
+	 * Invalidate any TLB address
+	 */
+	mov	r0, #0
+	stcopr	r0, TLBIMVA
+#endif
 	dsb	sy
 	bx	lr
 endfunc cortex_a57_disable_ext_debug
@@ -123,6 +130,49 @@ func check_errata_813420
 	b	cpu_rev_var_ls
 endfunc check_errata_813420
 
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A57 Errata #814670.
+	 * This applies only to revision r0p0 of Cortex A57.
+	 * Inputs:
+	 * r0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: r0-r3
+	 * ---------------------------------------------------
+	 */
+func errata_a57_814670_wa
+	/*
+	 * Compare r0 against revision r0p0
+	 */
+	mov		r2, lr
+	bl		check_errata_814670
+	cmp		r0, #ERRATA_NOT_APPLIES
+	beq		1f
+	ldcopr16	r0, r1, CORTEX_A57_CPUACTLR
+	orr64_imm	r0, r1, CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION
+	stcopr16	r0, r1, CORTEX_A57_CPUACTLR
+	isb
+1:
+	bx		r2
+endfunc errata_a57_814670_wa
+
+func check_errata_814670
+	mov	r1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_814670
+
+	/* ----------------------------------------------------
+	 * Errata Workaround for Cortex A57 Errata #817169.
+	 * This applies only to revision <= r0p1 of Cortex A57.
+	 * ----------------------------------------------------
+	 */
+func check_errata_817169
+	/*
+	 * Even though this is only needed for revision <= r0p1, it
+	 * is always applied because of the low cost of the workaround.
+	 */
+	mov	r0, #ERRATA_APPLIES
+	bx	lr
+endfunc check_errata_817169
+
 	/* --------------------------------------------------------------------
 	 * Disable the over-read from the LDNP instruction.
 	 *
@@ -366,6 +416,11 @@ func cortex_a57_reset_func
 	bl	errata_a57_813420_wa
 #endif
 
+#if ERRATA_A57_814670
+	mov	r0, r4
+	bl	errata_a57_814670_wa
+#endif
+
 #if A57_DISABLE_NON_TEMPORAL_HINT
 	mov	r0, r4
 	bl	a57_disable_ldnp_overread
@@ -533,6 +588,8 @@ func cortex_a57_errata_report
 	report_errata ERRATA_A57_806969, cortex_a57, 806969
 	report_errata ERRATA_A57_813419, cortex_a57, 813419
 	report_errata ERRATA_A57_813420, cortex_a57, 813420
+	report_errata ERRATA_A57_814670, cortex_a57, 814670
+	report_errata ERRATA_A57_817169, cortex_a57, 817169
 	report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
 		disable_ldnp_overread
 	report_errata ERRATA_A57_826974, cortex_a57, 826974
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 332bad75..f20082d2 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -42,6 +42,36 @@ func cortex_a53_disable_smp
 	ret
 endfunc cortex_a53_disable_smp
 
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A53 Errata #819472.
+	 * This applies only to revision <= r0p1 of Cortex A53.
+	 * ---------------------------------------------------
+	 */
+func check_errata_819472
+	/*
+	 * Even though this is only needed for revision <= r0p1, it
+	 * is always applied due to limitations of the current
+	 * errata framework.
+	 */
+	mov	x0, #ERRATA_APPLIES
+	ret
+endfunc check_errata_819472
+
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A53 Errata #824069.
+	 * This applies only to revision <= r0p2 of Cortex A53.
+	 * ---------------------------------------------------
+	 */
+func check_errata_824069
+	/*
+	 * Even though this is only needed for revision <= r0p2, it
+	 * is always applied due to limitations of the current
+	 * errata framework.
+	 */
+	mov	x0, #ERRATA_APPLIES
+	ret
+endfunc check_errata_824069
+
 	/* --------------------------------------------------
 	 * Errata Workaround for Cortex A53 Errata #826319.
 	 * This applies only to revision <= r0p2 of Cortex A53.
@@ -70,6 +100,21 @@ func check_errata_826319
 	b	cpu_rev_var_ls
 endfunc check_errata_826319
 
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A53 Errata #827319.
+	 * This applies only to revision <= r0p2 of Cortex A53.
+	 * ---------------------------------------------------
+	 */
+func check_errata_827319
+	/*
+	 * Even though this is only needed for revision <= r0p2, it
+	 * is always applied due to limitations of the current
+	 * errata framework.
+	 */
+	mov	x0, #ERRATA_APPLIES
+	ret
+endfunc check_errata_827319
+
 	/* ---------------------------------------------------------------------
 	 * Disable the cache non-temporal hint.
 	 *
@@ -304,7 +349,10 @@ func cortex_a53_errata_report
 	 * Report all errata. The revision-variant information is passed to
 	 * checking functions of each errata.
 	 */
+	report_errata ERRATA_A53_819472, cortex_a53, 819472
+	report_errata ERRATA_A53_824069, cortex_a53, 824069
 	report_errata ERRATA_A53_826319, cortex_a53, 826319
+	report_errata ERRATA_A53_827319, cortex_a53, 827319
 	report_errata ERRATA_A53_835769, cortex_a53, 835769
 	report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
 	report_errata ERRATA_A53_843419, cortex_a53, 843419
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index b347e299..1da80efa 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,11 +11,200 @@
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex A55 Errata #768277.
+	 * This applies only to revision r0p0 of Cortex A55.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_a55_768277_wa
+	/*
+	 * Compare x0 against revision r0p0
+	 */
+	mov	x17, x30
+	bl	check_errata_768277
+	cbz	x0, 1f
+	mrs	x1, CORTEX_A55_CPUACTLR_EL1
+	orr	x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+	msr	CORTEX_A55_CPUACTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a55_768277_wa
+
+func check_errata_768277
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_768277
+
+	/* ------------------------------------------------------------------
+	 * Errata Workaround for Cortex A55 Errata #778703.
+	 * This applies only to revision r0p0 of Cortex A55 where L2 cache is
+	 * not configured.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * ------------------------------------------------------------------
+	 */
+func errata_a55_778703_wa
+	/*
+	 * Compare x0 against revision r0p0 and check that no private L2 cache
+	 * is configured
+	 */
+	mov	x17, x30
+	bl	check_errata_778703
+	cbz	x0, 1f
+	mrs	x1, CORTEX_A55_CPUECTLR_EL1
+	orr	x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
+	msr	CORTEX_A55_CPUECTLR_EL1, x1
+	mrs	x1, CORTEX_A55_CPUACTLR_EL1
+	orr	x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
+	msr	CORTEX_A55_CPUACTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a55_778703_wa
+
+func check_errata_778703
+	mov	x16, x30
+	mov	x1, #0x00
+	bl	cpu_rev_var_ls
+	/*
+	 * Check that no private L2 cache is configured
+	 */
+	mrs	x1, CORTEX_A55_CLIDR_EL1
+	and	x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3
+	cmp	x1, #0
+	mov	x2, #ERRATA_NOT_APPLIES
+	csel	x0, x0, x2, eq
+	ret	x16
+endfunc check_errata_778703
+
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex A55 Errata #798797.
+	 * This applies only to revision r0p0 of Cortex A55.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_a55_798797_wa
+	/*
+	 * Compare x0 against revision r0p0
+	 */
+	mov	x17, x30
+	bl	check_errata_798797
+	cbz	x0, 1f
+	mrs	x1, CORTEX_A55_CPUACTLR_EL1
+	orr	x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+	msr	CORTEX_A55_CPUACTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a55_798797_wa
+
+func check_errata_798797
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_798797
+
+	/* --------------------------------------------------------------------
+	 * Errata Workaround for Cortex A55 Errata #846532.
+	 * This applies only to revisions <= r0p1 of Cortex A55.
+	 * Disabling dual-issue has a small impact on performance. Disabling a
+	 * power optimization feature is an alternate workaround with no impact
+	 * on performance but with an increase in power consumption (see errata
+	 * notice).
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------------------------
+	 */
+func errata_a55_846532_wa
+	/*
+	 * Compare x0 against revision r0p1
+	 */
+	mov	x17, x30
+	bl	check_errata_846532
+	cbz	x0, 1f
+	mrs	x1, CORTEX_A55_CPUACTLR_EL1
+	orr	x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+	msr	CORTEX_A55_CPUACTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a55_846532_wa
+
+func check_errata_846532
+	mov	x1, #0x01
+	b	cpu_rev_var_ls
+endfunc check_errata_846532
+
+	/* -----------------------------------------------------
+	 * Errata Workaround for Cortex A55 Errata #903758.
+	 * This applies only to revisions <= r0p1 of Cortex A55.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * -----------------------------------------------------
+	 */
+func errata_a55_903758_wa
+	/*
+	 * Compare x0 against revision r0p1
+	 */
+	mov	x17, x30
+	bl	check_errata_903758
+	cbz	x0, 1f
+	mrs	x1, CORTEX_A55_CPUACTLR_EL1
+	orr	x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+	msr	CORTEX_A55_CPUACTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a55_903758_wa
+
+func check_errata_903758
+	mov	x1, #0x01
+	b	cpu_rev_var_ls
+endfunc check_errata_903758
+
 func cortex_a55_reset_func
 	mov	x19, x30
+
 #if ERRATA_DSU_936184
 	bl	errata_dsu_936184_wa
 #endif
+
+	bl	cpu_get_rev_var
+	mov	x18, x0
+
+#if ERRATA_A55_768277
+	mov	x0, x18
+	bl	errata_a55_768277_wa
+#endif
+
+#if ERRATA_A55_778703
+	mov	x0, x18
+	bl	errata_a55_778703_wa
+#endif
+
+#if ERRATA_A55_798797
+	mov	x0, x18
+	bl	errata_a55_798797_wa
+#endif
+
+#if ERRATA_A55_846532
+	mov	x0, x18
+	bl	errata_a55_846532_wa
+#endif
+
+#if ERRATA_A55_903758
+	mov	x0, x18
+	bl	errata_a55_903758_wa
+#endif
+
 	ret	x19
 endfunc cortex_a55_reset_func
 
@@ -49,6 +238,11 @@ func cortex_a55_errata_report
 	 * "report_errata" is expecting it and it doesn't corrupt it.
 	 */
 	report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
+	report_errata ERRATA_A55_768277, cortex_a55, 768277
+	report_errata ERRATA_A55_778703, cortex_a55, 778703
+	report_errata ERRATA_A55_798797, cortex_a55, 798797
+	report_errata ERRATA_A55_846532, cortex_a55, 846532
+	report_errata ERRATA_A55_903758, cortex_a55, 903758
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index a8626716..dd03c0f0 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -59,6 +59,13 @@ func cortex_a57_disable_ext_debug
 	mov	x0, #1
 	msr	osdlr_el1, x0
 	isb
+#if ERRATA_A57_817169
+	/*
+	 * Invalidate any TLB address
+	 */
+	mov	x0, #0
+	tlbi	vae3, x0
+#endif
 	dsb	sy
 	ret
 endfunc cortex_a57_disable_ext_debug
@@ -132,6 +139,48 @@ func check_errata_813420
 	b	cpu_rev_var_ls
 endfunc check_errata_813420
 
+	/* ---------------------------------------------------
+	 * Errata Workaround for Cortex A57 Errata #814670.
+	 * This applies only to revision r0p0 of Cortex A57.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * ---------------------------------------------------
+	 */
+func errata_a57_814670_wa
+	/*
+	 * Compare x0 against revision r0p0
+	 */
+	mov	x17, x30
+	bl	check_errata_814670
+	cbz	x0, 1f
+	mrs	x1, CORTEX_A57_CPUACTLR_EL1
+	orr	x1, x1, #CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION
+	msr	CORTEX_A57_CPUACTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a57_814670_wa
+
+func check_errata_814670
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_814670
+
+	/* ----------------------------------------------------
+	 * Errata Workaround for Cortex A57 Errata #817169.
+	 * This applies only to revision <= r0p1 of Cortex A57.
+	 * ----------------------------------------------------
+	 */
+func check_errata_817169
+	/*
+	 * Even though this is only needed for revision <= r0p1, it
+	 * is always applied because of the low cost of the workaround.
+	 */
+	mov	x0, #ERRATA_APPLIES
+	ret
+endfunc check_errata_817169
+
 	/* --------------------------------------------------------------------
 	 * Disable the over-read from the LDNP instruction.
 	 *
@@ -366,6 +415,11 @@ func cortex_a57_reset_func
 	bl	errata_a57_813420_wa
 #endif
 
+#if ERRATA_A57_814670
+	mov	x0, x18
+	bl	errata_a57_814670_wa
+#endif
+
 #if A57_DISABLE_NON_TEMPORAL_HINT
 	mov	x0, x18
 	bl	a57_disable_ldnp_overread
@@ -537,6 +591,8 @@ func cortex_a57_errata_report
 	report_errata ERRATA_A57_806969, cortex_a57, 806969
 	report_errata ERRATA_A57_813419, cortex_a57, 813419
 	report_errata ERRATA_A57_813420, cortex_a57, 813420
+	report_errata ERRATA_A57_814670, cortex_a57, 814670
+	report_errata ERRATA_A57_817169, cortex_a57, 817169
 	report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \
 		disable_ldnp_overread
 	report_errata ERRATA_A57_826974, cortex_a57, 826974
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 02208f0e..2d3984e1 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -53,10 +53,22 @@ endif
 # These should be enabled by the platform if the erratum workaround needs to be
 # applied.
 
+# Flag to apply erratum 819472 workaround during reset. This erratum applies
+# only to revision <= r0p1 of the Cortex A53 cpu.
+ERRATA_A53_819472	?=0
+
+# Flag to apply erratum 824069 workaround during reset. This erratum applies
+# only to revision <= r0p2 of the Cortex A53 cpu.
+ERRATA_A53_824069	?=0
+
 # Flag to apply erratum 826319 workaround during reset. This erratum applies
 # only to revision <= r0p2 of the Cortex A53 cpu.
 ERRATA_A53_826319	?=0
 
+# Flag to apply erratum 827319 workaround during reset. This erratum applies
+# only to revision <= r0p2 of the Cortex A53 cpu.
+ERRATA_A53_827319	?=0
+
 # Flag to apply erratum 835769 workaround at compile and link time.  This
 # erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
 # workaround can lead the linker to create "*.stub" sections.
@@ -79,6 +91,26 @@ ERRATA_A53_843419	?=0
 # of by the rich OS.
 ERRATA_A53_855873	?=0
 
+# Flag to apply erratum 768277 workaround during reset. This erratum applies
+# only to revision r0p0 of the Cortex A55 cpu.
+ERRATA_A55_768277	?=0
+
+# Flag to apply erratum 778703 workaround during reset. This erratum applies
+# only to revision r0p0 of the Cortex A55 cpu.
+ERRATA_A55_778703	?=0
+
+# Flag to apply erratum 798797 workaround during reset. This erratum applies
+# only to revision r0p0 of the Cortex A55 cpu.
+ERRATA_A55_798797	?=0
+
+# Flag to apply erratum 846532 workaround during reset. This erratum applies
+# only to revision <= r0p1 of the Cortex A55 cpu.
+ERRATA_A55_846532	?=0
+
+# Flag to apply erratum 903758 workaround during reset. This erratum applies
+# only to revision <= r0p1 of the Cortex A55 cpu.
+ERRATA_A55_903758	?=0
+
 # Flag to apply erratum 806969 workaround during reset. This erratum applies
 # only to revision r0p0 of the Cortex A57 cpu.
 ERRATA_A57_806969	?=0
@@ -91,6 +123,14 @@ ERRATA_A57_813419	?=0
 # only to revision r0p0 of the Cortex A57 cpu.
 ERRATA_A57_813420	?=0
 
+# Flag to apply erratum 814670  workaround during reset. This erratum applies
+# only to revision r0p0 of the Cortex A57 cpu.
+ERRATA_A57_814670	?=0
+
+# Flag to apply erratum 817169 workaround during power down. This erratum
+# applies only to revision <= r0p1 of the Cortex A57 cpu.
+ERRATA_A57_817169	?=0
+
 # Flag to apply erratum 826974 workaround during reset. This erratum applies
 # only to revision <= r1p1 of the Cortex A57 cpu.
 ERRATA_A57_826974	?=0
@@ -152,10 +192,22 @@ ERRATA_N1_1043202	?=1
 # higher DSU power consumption on idle.
 ERRATA_DSU_936184	?=0
 
+# Process ERRATA_A53_819472 flag
+$(eval $(call assert_boolean,ERRATA_A53_819472))
+$(eval $(call add_define,ERRATA_A53_819472))
+
+# Process ERRATA_A53_824069 flag
+$(eval $(call assert_boolean,ERRATA_A53_824069))
+$(eval $(call add_define,ERRATA_A53_824069))
+
 # Process ERRATA_A53_826319 flag
 $(eval $(call assert_boolean,ERRATA_A53_826319))
 $(eval $(call add_define,ERRATA_A53_826319))
 
+# Process ERRATA_A53_827319 flag
+$(eval $(call assert_boolean,ERRATA_A53_827319))
+$(eval $(call add_define,ERRATA_A53_827319))
+
 # Process ERRATA_A53_835769 flag
 $(eval $(call assert_boolean,ERRATA_A53_835769))
 $(eval $(call add_define,ERRATA_A53_835769))
@@ -172,6 +224,26 @@ $(eval $(call add_define,ERRATA_A53_843419))
 $(eval $(call assert_boolean,ERRATA_A53_855873))
 $(eval $(call add_define,ERRATA_A53_855873))
 
+# Process ERRATA_A55_768277 flag
+$(eval $(call assert_boolean,ERRATA_A55_768277))
+$(eval $(call add_define,ERRATA_A55_768277))
+
+# Process ERRATA_A55_778703 flag
+$(eval $(call assert_boolean,ERRATA_A55_778703))
+$(eval $(call add_define,ERRATA_A55_778703))
+
+# Process ERRATA_A55_798797 flag
+$(eval $(call assert_boolean,ERRATA_A55_798797))
+$(eval $(call add_define,ERRATA_A55_798797))
+
+# Process ERRATA_A55_846532 flag
+$(eval $(call assert_boolean,ERRATA_A55_846532))
+$(eval $(call add_define,ERRATA_A55_846532))
+
+# Process ERRATA_A55_903758 flag
+$(eval $(call assert_boolean,ERRATA_A55_903758))
+$(eval $(call add_define,ERRATA_A55_903758))
+
 # Process ERRATA_A57_806969 flag
 $(eval $(call assert_boolean,ERRATA_A57_806969))
 $(eval $(call add_define,ERRATA_A57_806969))
@@ -184,6 +256,14 @@ $(eval $(call add_define,ERRATA_A57_813419))
 $(eval $(call assert_boolean,ERRATA_A57_813420))
 $(eval $(call add_define,ERRATA_A57_813420))
 
+# Process ERRATA_A57_814670 flag
+$(eval $(call assert_boolean,ERRATA_A57_814670))
+$(eval $(call add_define,ERRATA_A57_814670))
+
+# Process ERRATA_A57_817169 flag
+$(eval $(call assert_boolean,ERRATA_A57_817169))
+$(eval $(call add_define,ERRATA_A57_817169))
+
 # Process ERRATA_A57_826974 flag
 $(eval $(call assert_boolean,ERRATA_A57_826974))
 $(eval $(call add_define,ERRATA_A57_826974))