diff options
| author | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-02-28 16:23:53 +0000 |
|---|---|---|
| committer | Ambroise Vincent <ambroise.vincent@arm.com> | 2019-03-13 15:40:45 +0000 |
| commit | 0b64c194853d631909317c041d5501ec53c3bfef (patch) | |
| tree | 5ec144b07f2deb1fefa2ab8106945c51ab2853f5 /lib | |
| parent | ab15922ebd2db1783dbd4db571b582263f8d33ea (diff) | |
Cortex-A17: Implement workaround for errata 852421
Change-Id: Ic3004fc43229d63c5a59ca74c1837fb0604e1f33
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a17.S | 40 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
2 files changed, 47 insertions, 1 deletions
diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S index b84c1267..87e8c8d0 100644 --- a/lib/cpus/aarch32/cortex_a17.S +++ b/lib/cpus/aarch32/cortex_a17.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,6 +35,34 @@ func cortex_a17_enable_smp bx lr endfunc cortex_a17_enable_smp + /* ---------------------------------------------------- + * Errata Workaround for Cortex A17 Errata #852421. + * This applies only to revision <= r1p2 of Cortex A17. + * Inputs: + * r0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: r0-r3 + * ---------------------------------------------------- + */ +func errata_a17_852421_wa + /* + * Compare r0 against revision r1p2 + */ + mov r2, lr + bl check_errata_852421 + cmp r0, #ERRATA_NOT_APPLIES + beq 1f + ldcopr r0, CORTEX_A17_IMP_DEF_REG1 + orr r0, r0, #(1<<24) + stcopr r0, CORTEX_A17_IMP_DEF_REG1 +1: + bx r2 +endfunc errata_a17_852421_wa + +func check_errata_852421 + mov r1, #0x12 + b cpu_rev_var_ls +endfunc check_errata_852421 + func check_errata_cve_2017_5715 #if WORKAROUND_CVE_2017_5715 mov r0, #ERRATA_APPLIES @@ -58,6 +86,7 @@ func cortex_a17_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A17_852421, cortex_a17, 852421 report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715 pop {r12, lr} @@ -66,12 +95,21 @@ endfunc cortex_a17_errata_report #endif func cortex_a17_reset_func + mov r5, lr + bl cpu_get_rev_var + +#if ERRATA_A17_852421 + bl errata_a17_852421_wa +#endif + #if IMAGE_BL32 && WORKAROUND_CVE_2017_5715 ldr r0, =workaround_bpiall_runtime_exceptions stcopr r0, VBAR stcopr r0, MVBAR /* isb will be applied in the course of the reset func */ #endif + + mov lr, r5 b cortex_a17_enable_smp endfunc cortex_a17_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index f178f1af..9ccd7877 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -61,6 +61,10 @@ ERRATA_A15_816470 ?=0 # only to revision >= r3p0 of the Cortex A15 cpu. ERRATA_A15_827671 ?=0 +# Flag to apply erratum 852421 workaround during reset. This erratum applies +# only to revision <= r1p2 of the Cortex A17 cpu. +ERRATA_A17_852421 ?=0 + # Flag to apply erratum 819472 workaround during reset. This erratum applies # only to revision <= r0p1 of the Cortex A53 cpu. ERRATA_A53_819472 ?=0 @@ -212,6 +216,10 @@ $(eval $(call add_define,ERRATA_A15_816470)) $(eval $(call assert_boolean,ERRATA_A15_827671)) $(eval $(call add_define,ERRATA_A15_827671)) +# Process ERRATA_A17_852421 flag +$(eval $(call assert_boolean,ERRATA_A17_852421)) +$(eval $(call add_define,ERRATA_A17_852421)) + # Process ERRATA_A53_819472 flag $(eval $(call assert_boolean,ERRATA_A53_819472)) $(eval $(call add_define,ERRATA_A53_819472)) |