diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2017-12-17 16:20:50 +0000 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2018-01-16 17:45:50 +0000 |
| commit | fe3ee5530a8d0d0b6a478167125d00c40f294a86 (patch) | |
| tree | cf464cd1c9cbf17a7312e4c42cb4b4875da70f34 /xen/include/asm-x86/cpufeature.h | |
| parent | 31d6c53adf6417bf449ca50e8416e41b64d46803 (diff) | |
x86/amd: Try to set lfence as being Dispatch Serialising
This property is required for the AMD's recommended mitigation for Branch
Target Injection, but Xen needs to cope with being unable to detect or modify
the MSR.
This is part of XSA-254.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/include/asm-x86/cpufeature.h')
| -rw-r--r-- | xen/include/asm-x86/cpufeature.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 84cc51d2bd..adc333f20e 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -104,6 +104,7 @@ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) #define cpu_has_aperfmperf boot_cpu_has(X86_FEATURE_APERFMPERF) +#define cpu_has_lfence_dispatch boot_cpu_has(X86_FEATURE_LFENCE_DISPATCH) enum _cache_type { CACHE_TYPE_NULL = 0, |