From fe3ee5530a8d0d0b6a478167125d00c40f294a86 Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Sun, 17 Dec 2017 16:20:50 +0000 Subject: x86/amd: Try to set lfence as being Dispatch Serialising This property is required for the AMD's recommended mitigation for Branch Target Injection, but Xen needs to cope with being unable to detect or modify the MSR. This is part of XSA-254. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- xen/include/asm-x86/cpufeature.h | 1 + 1 file changed, 1 insertion(+) (limited to 'xen/include/asm-x86/cpufeature.h') diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 84cc51d2bd..adc333f20e 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -104,6 +104,7 @@ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) #define cpu_has_aperfmperf boot_cpu_has(X86_FEATURE_APERFMPERF) +#define cpu_has_lfence_dispatch boot_cpu_has(X86_FEATURE_LFENCE_DISPATCH) enum _cache_type { CACHE_TYPE_NULL = 0, -- cgit v1.2.3