diff options
| author | Erwan Gouriou <erwan.gouriou@linaro.org> | 2017-02-20 11:34:00 +0100 |
|---|---|---|
| committer | Anas Nashif <nashif@linux.intel.com> | 2017-02-23 13:13:28 +0000 |
| commit | d17f16d8d7bf80b978a11044b3aa9c75bd5ff761 (patch) | |
| tree | c4f3a5214da05217c2f411574e5bde5462073230 | |
| parent | 1d32ad0dc38268567e3a47586ef5e229e11c20e9 (diff) | |
gpio: enable ports F G (and H) for stm32f1xx (stm32f4xx)
Some GPIO ports activation where missing since not used
on available soc/boards.
Since stm32 family increases, activation of these ports
should be made available.
Jira: ZEP-1551
Change-Id: I612d135b28ef255bc771599e33796671ff81d0ac
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
| -rw-r--r-- | drivers/gpio/gpio_stm32.c | 33 | ||||
| -rw-r--r-- | include/drivers/clock_control/stm32f1_clock_control.h | 2 |
2 files changed, 32 insertions, 3 deletions
diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index 0de0ea2ba..6e4619db2 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -335,15 +335,42 @@ GPIO_DEVICE_INIT("GPIOE", e, GPIOE_BASE, STM32_PORTE, #ifdef CONFIG_GPIO_STM32_PORTF GPIO_DEVICE_INIT("GPIOF", f, GPIOF_BASE, STM32_PORTF, - STM32_PERIPH_GPIOF, STM32_CLOCK_BUS_GPIO); +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE + STM32_PERIPH_GPIOF, STM32_CLOCK_BUS_GPIO +#else +#ifdef CONFIG_SOC_SERIES_STM32F1X + STM32F10X_CLOCK_SUBSYS_IOPF + | STM32F10X_CLOCK_SUBSYS_AFIO +#elif CONFIG_SOC_SERIES_STM32F4X + STM32F4X_CLOCK_ENABLE_GPIOF +#endif +#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ + ); #endif /* CONFIG_GPIO_STM32_PORTF */ #ifdef CONFIG_GPIO_STM32_PORTG GPIO_DEVICE_INIT("GPIOG", g, GPIOG_BASE, STM32_PORTG, - STM32_PERIPH_GPIOG, STM32_CLOCK_BUS_GPIO); +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE + STM32_PERIPH_GPIOG, STM32_CLOCK_BUS_GPIO +#else +#ifdef CONFIG_SOC_SERIES_STM32F1X + STM32F10X_CLOCK_SUBSYS_IOPG + | STM32F10X_CLOCK_SUBSYS_AFIO +#elif CONFIG_SOC_SERIES_STM32F4X + STM32F4X_CLOCK_ENABLE_GPIOG +#endif +#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ + ); #endif /* CONFIG_GPIO_STM32_PORTG */ #ifdef CONFIG_GPIO_STM32_PORTH GPIO_DEVICE_INIT("GPIOH", h, GPIOH_BASE, STM32_PORTH, - STM32_PERIPH_GPIOH, STM32_CLOCK_BUS_GPIO); +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE + STM32_PERIPH_GPIOH, STM32_CLOCK_BUS_GPIO +#else +#ifdef CONFIG_SOC_SERIES_STM32F4X + STM32F4X_CLOCK_ENABLE_GPIOH +#endif +#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ + ); #endif /* CONFIG_GPIO_STM32_PORTH */ diff --git a/include/drivers/clock_control/stm32f1_clock_control.h b/include/drivers/clock_control/stm32f1_clock_control.h index 75c9629a6..891843356 100644 --- a/include/drivers/clock_control/stm32f1_clock_control.h +++ b/include/drivers/clock_control/stm32f1_clock_control.h @@ -43,6 +43,8 @@ enum { STM32F10X_CLOCK_SUBSYS_IOPC = STM32F10X_CLOCK_APB2_BASE | 1 << 4, STM32F10X_CLOCK_SUBSYS_IOPD = STM32F10X_CLOCK_APB2_BASE | 1 << 5, STM32F10X_CLOCK_SUBSYS_IOPE = STM32F10X_CLOCK_APB2_BASE | 1 << 6, + STM32F10X_CLOCK_SUBSYS_IOPF = STM32F10X_CLOCK_APB2_BASE | 1 << 7, + STM32F10X_CLOCK_SUBSYS_IOPG = STM32F10X_CLOCK_APB2_BASE | 1 << 8, STM32F10X_CLOCK_SUBSYS_ADC1 = STM32F10X_CLOCK_APB2_BASE | 1 << 9, STM32F10X_CLOCK_SUBSYS_ADC2 = STM32F10X_CLOCK_APB2_BASE | 1 << 10, STM32F10X_CLOCK_SUBSYS_TIM1 = STM32F10X_CLOCK_APB2_BASE | 1 << 11, |