diff options
Diffstat (limited to 'ports/stm32/mpu.h')
| -rw-r--r-- | ports/stm32/mpu.h | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/ports/stm32/mpu.h b/ports/stm32/mpu.h index 74ba81496..ff51f382e 100644 --- a/ports/stm32/mpu.h +++ b/ports/stm32/mpu.h @@ -36,39 +36,39 @@ #define MPU_REGION_SDRAM2 (MPU_REGION_NUMBER5) #define MPU_CONFIG_DISABLE(srd, size) ( \ - MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \ - | MPU_REGION_NO_ACCESS << MPU_RASR_AP_Pos \ - | MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos \ - | MPU_ACCESS_NOT_SHAREABLE << MPU_RASR_S_Pos \ - | MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos \ - | MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos \ - | (srd) << MPU_RASR_SRD_Pos \ - | (size) << MPU_RASR_SIZE_Pos \ - | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ + MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \ + | MPU_REGION_NO_ACCESS << MPU_RASR_AP_Pos \ + | MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos \ + | MPU_ACCESS_NOT_SHAREABLE << MPU_RASR_S_Pos \ + | MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos \ + | MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos \ + | (srd) << MPU_RASR_SRD_Pos \ + | (size) << MPU_RASR_SIZE_Pos \ + | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ ) #define MPU_CONFIG_ETH(size) ( \ - MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \ - | MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos \ - | MPU_TEX_LEVEL1 << MPU_RASR_TEX_Pos \ - | MPU_ACCESS_SHAREABLE << MPU_RASR_S_Pos \ - | MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos \ - | MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos \ - | 0x00 << MPU_RASR_SRD_Pos \ - | (size) << MPU_RASR_SIZE_Pos \ - | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ + MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \ + | MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos \ + | MPU_TEX_LEVEL1 << MPU_RASR_TEX_Pos \ + | MPU_ACCESS_SHAREABLE << MPU_RASR_S_Pos \ + | MPU_ACCESS_NOT_CACHEABLE << MPU_RASR_C_Pos \ + | MPU_ACCESS_NOT_BUFFERABLE << MPU_RASR_B_Pos \ + | 0x00 << MPU_RASR_SRD_Pos \ + | (size) << MPU_RASR_SIZE_Pos \ + | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ ) #define MPU_CONFIG_SDRAM(size) ( \ - MPU_INSTRUCTION_ACCESS_ENABLE << MPU_RASR_XN_Pos \ - | MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos \ - | MPU_TEX_LEVEL1 << MPU_RASR_TEX_Pos \ - | MPU_ACCESS_NOT_SHAREABLE << MPU_RASR_S_Pos \ - | MPU_ACCESS_CACHEABLE << MPU_RASR_C_Pos \ - | MPU_ACCESS_BUFFERABLE << MPU_RASR_B_Pos \ - | 0x00 << MPU_RASR_SRD_Pos \ - | (size) << MPU_RASR_SIZE_Pos \ - | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ + MPU_INSTRUCTION_ACCESS_ENABLE << MPU_RASR_XN_Pos \ + | MPU_REGION_FULL_ACCESS << MPU_RASR_AP_Pos \ + | MPU_TEX_LEVEL1 << MPU_RASR_TEX_Pos \ + | MPU_ACCESS_NOT_SHAREABLE << MPU_RASR_S_Pos \ + | MPU_ACCESS_CACHEABLE << MPU_RASR_C_Pos \ + | MPU_ACCESS_BUFFERABLE << MPU_RASR_B_Pos \ + | 0x00 << MPU_RASR_SRD_Pos \ + | (size) << MPU_RASR_SIZE_Pos \ + | MPU_REGION_ENABLE << MPU_RASR_ENABLE_Pos \ ) static inline void mpu_init(void) { |