diff options
Diffstat (limited to 'ports/stm32/eth.c')
| -rw-r--r-- | ports/stm32/eth.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/ports/stm32/eth.c b/ports/stm32/eth.c index 756bb6dd6..33d20707e 100644 --- a/ports/stm32/eth.c +++ b/ports/stm32/eth.c @@ -256,15 +256,15 @@ STATIC int eth_mac_init(eth_t *self) { ETH->DMAIER = ETH_DMAIER_NISE // enable normal interrupts | ETH_DMAIER_RIE // enable RX interrupt - ; + ; // Configure RX descriptor lists for (size_t i = 0; i < RX_BUF_NUM; ++i) { eth_dma.rx_descr[i].rdes0 = 1 << RX_DESCR_0_OWN_Pos; eth_dma.rx_descr[i].rdes1 = 1 << RX_DESCR_1_RCH_Pos // chained - | RX_BUF_SIZE << RX_DESCR_1_RBS1_Pos - ; + | RX_BUF_SIZE << RX_DESCR_1_RBS1_Pos + ; eth_dma.rx_descr[i].rdes2 = (uint32_t)ð_dma.rx_buf[i * RX_BUF_SIZE]; eth_dma.rx_descr[i].rdes3 = (uint32_t)ð_dma.rx_descr[(i + 1) % RX_BUF_NUM]; } @@ -285,13 +285,13 @@ STATIC int eth_mac_init(eth_t *self) { ETH->DMAOMR = ETH_DMAOMR_RSF // read from RX FIFO after a full frame is written | ETH_DMAOMR_TSF // transmit when a full frame is in TX FIFO (needed by errata) - ; + ; mp_hal_delay_ms(2); // Select MAC filtering options ETH->MACFFR = ETH_MACFFR_RA // pass all frames up - ; + ; mp_hal_delay_ms(2); // Set MAC address @@ -307,21 +307,21 @@ STATIC int eth_mac_init(eth_t *self) { : (phy_scsr & PHY_SCSR_SPEED_Msk) == PHY_SCSR_SPEED_100HALF ? ETH_MACCR_FES : (phy_scsr & PHY_SCSR_SPEED_Msk) == PHY_SCSR_SPEED_100FULL ? (ETH_MACCR_FES | ETH_MACCR_DM) : 0 - ; + ; mp_hal_delay_ms(2); // Start MAC layer ETH->MACCR |= ETH_MACCR_TE // enable TX | ETH_MACCR_RE // enable RX - ; + ; mp_hal_delay_ms(2); // Start DMA layer ETH->DMAOMR |= ETH_DMAOMR_ST // start TX | ETH_DMAOMR_SR // start RX - ; + ; mp_hal_delay_ms(2); // Enable interrupts @@ -373,11 +373,11 @@ STATIC int eth_tx_buf_send(void) { // Schedule to send next outgoing frame tx_descr->tdes0 = 1 << TX_DESCR_0_OWN_Pos // owned by DMA - | 1 << TX_DESCR_0_LS_Pos // last segment - | 1 << TX_DESCR_0_FS_Pos // first segment - | 3 << TX_DESCR_0_CIC_Pos // enable all checksums inserted by hardware - | 1 << TX_DESCR_0_TCH_Pos // TX descriptor is chained - ; + | 1 << TX_DESCR_0_LS_Pos // last segment + | 1 << TX_DESCR_0_FS_Pos // first segment + | 3 << TX_DESCR_0_CIC_Pos // enable all checksums inserted by hardware + | 1 << TX_DESCR_0_TCH_Pos // TX descriptor is chained + ; // Notify ETH DMA that there is a new TX descriptor for sending __DMB(); @@ -398,8 +398,8 @@ STATIC void eth_dma_rx_free(void) { // Schedule to get next incoming frame rx_descr->rdes1 = 1 << RX_DESCR_1_RCH_Pos // RX descriptor is chained - | RX_BUF_SIZE << RX_DESCR_1_RBS1_Pos // maximum buffer length - ; + | RX_BUF_SIZE << RX_DESCR_1_RBS1_Pos // maximum buffer length + ; rx_descr->rdes2 = (uint32_t)buf; rx_descr->rdes3 = (uint32_t)ð_dma.rx_descr[eth_dma.rx_descr_idx]; rx_descr->rdes0 = 1 << RX_DESCR_0_OWN_Pos; // owned by DMA @@ -424,7 +424,7 @@ void ETH_IRQHandler(void) { // Get RX buffer containing new frame size_t len = (rx_descr->rdes0 & RX_DESCR_0_FL_Msk) >> RX_DESCR_0_FL_Pos; len -= 4; // discard CRC at end - uint8_t *buf = (uint8_t*)rx_descr->rdes2; + uint8_t *buf = (uint8_t *)rx_descr->rdes2; // Process frame eth_process_frame(ð_instance, len, buf); |