7029017: Additional architecture support for c2 compiler

Summary: Enables cross building of a c2 VM. Support masking of shift counts when the processor architecture mandates it.
Reviewed-by: kvn, never

6 files changed, 47 insertions, 1 deletions

diff --git a/src/share/vm/adlc/main.cpp b/src/share/vm/adlc/main.cpp
index 3d74a4f02..88a75e684 100644
--- a/src/share/vm/adlc/main.cpp
+++ b/src/share/vm/adlc/main.cpp
@@ -240,6 +240,11 @@ int main(int argc, char *argv[])
   AD.addInclude(AD._CPP_file, "nativeInst_sparc.hpp");
   AD.addInclude(AD._CPP_file, "vmreg_sparc.inline.hpp");
 #endif
+#ifdef TARGET_ARCH_arm
+  AD.addInclude(AD._CPP_file, "assembler_arm.inline.hpp");
+  AD.addInclude(AD._CPP_file, "nativeInst_arm.hpp");
+  AD.addInclude(AD._CPP_file, "vmreg_arm.inline.hpp");
+#endif
   AD.addInclude(AD._HPP_file, "memory/allocation.hpp");
   AD.addInclude(AD._HPP_file, "opto/machnode.hpp");
   AD.addInclude(AD._HPP_file, "opto/node.hpp");
diff --git a/src/share/vm/opto/chaitin.cpp b/src/share/vm/opto/chaitin.cpp
index 6108084f9..3c363e9ff 100644
--- a/src/share/vm/opto/chaitin.cpp
+++ b/src/share/vm/opto/chaitin.cpp
@@ -673,7 +673,7 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
         case Op_RegD:
           lrg.set_num_regs(2);
           // Define platform specific register pressure
-#ifdef SPARC
+#if defined(SPARC) || defined(ARM)
           lrg.set_reg_pressure(2);
 #elif defined(IA32)
           if( ireg == Op_RegL ) {
diff --git a/src/share/vm/opto/compile.cpp b/src/share/vm/opto/compile.cpp
index c9e04bb7a..39bcf30bd 100644
--- a/src/share/vm/opto/compile.cpp
+++ b/src/share/vm/opto/compile.cpp
@@ -2544,6 +2544,36 @@ static void final_graph_reshaping_impl( Node *n, Final_Reshape_Counts &frc ) {
       frc.inc_inner_loop_count();
     }
     break;
+  case Op_LShiftI:
+  case Op_RShiftI:
+  case Op_URShiftI:
+  case Op_LShiftL:
+  case Op_RShiftL:
+  case Op_URShiftL:
+    if (Matcher::need_masked_shift_count) {
+      // The cpu's shift instructions don't restrict the count to the
+      // lower 5/6 bits. We need to do the masking ourselves.
+      Node* in2 = n->in(2);
+      juint mask = (n->bottom_type() == TypeInt::INT) ? (BitsPerInt - 1) : (BitsPerLong - 1);
+      const TypeInt* t = in2->find_int_type();
+      if (t != NULL && t->is_con()) {
+        juint shift = t->get_con();
+        if (shift > mask) { // Unsigned cmp
+          Compile* C = Compile::current();
+          n->set_req(2, ConNode::make(C, TypeInt::make(shift & mask)));
+        }
+      } else {
+        if (t == NULL || t->_lo < 0 || t->_hi > (int)mask) {
+          Compile* C = Compile::current();
+          Node* shift = new (C, 3) AndINode(in2, ConNode::make(C, TypeInt::make(mask)));
+          n->set_req(2, shift);
+        }
+      }
+      if (in2->outcnt() == 0) { // Remove dead node
+        in2->disconnect_inputs(NULL);
+      }
+    }
+    break;
   default:
     assert( !n->is_Call(), "" );
     assert( !n->is_Mem(), "" );
diff --git a/src/share/vm/opto/lcm.cpp b/src/share/vm/opto/lcm.cpp
index 3d84f6baf..fd3343c3c 100644
--- a/src/share/vm/opto/lcm.cpp
+++ b/src/share/vm/opto/lcm.cpp
@@ -42,6 +42,9 @@
 #ifdef TARGET_ARCH_MODEL_zero
 # include "adfiles/ad_zero.hpp"
 #endif
+#ifdef TARGET_ARCH_MODEL_arm
+# include "adfiles/ad_arm.hpp"
+#endif
 
 // Optimization - Graph Style
 
diff --git a/src/share/vm/opto/matcher.cpp b/src/share/vm/opto/matcher.cpp
index 2bd3acd6f..48ff22d10 100644
--- a/src/share/vm/opto/matcher.cpp
+++ b/src/share/vm/opto/matcher.cpp
@@ -49,6 +49,9 @@
 #ifdef TARGET_ARCH_MODEL_zero
 # include "adfiles/ad_zero.hpp"
 #endif
+#ifdef TARGET_ARCH_MODEL_arm
+# include "adfiles/ad_arm.hpp"
+#endif
 
 OptoReg::Name OptoReg::c_frame_pointer;
 
diff --git a/src/share/vm/opto/matcher.hpp b/src/share/vm/opto/matcher.hpp
index c1627c60f..e8d3c99f8 100644
--- a/src/share/vm/opto/matcher.hpp
+++ b/src/share/vm/opto/matcher.hpp
@@ -427,6 +427,11 @@ public:
   // Do ints take an entire long register or just half?
   static const bool int_in_long;
 
+  // Do the processor's shift instructions only use the low 5/6 bits
+  // of the count for 32/64 bit ints? If not we need to do the masking
+  // ourselves.
+  static const bool need_masked_shift_count;
+
   // This routine is run whenever a graph fails to match.
   // If it returns, the compiler should bailout to interpreter without error.
   // In non-product mode, SoftMatchFailure is false to detect non-canonical