diff options
| author | goetz <none@none> | 2014-01-16 14:25:51 +0100 |
|---|---|---|
| committer | goetz <none@none> | 2014-01-16 14:25:51 +0100 |
| commit | e9ad79c653c20256fe759ebadd1dbbd7424d588f (patch) | |
| tree | e8cc1dc6192f663c1f5abeb9f37ae854797b3fb4 /src/share/vm/utilities | |
| parent | dc222326a7025dd7da0c1d7209c78654e76956a2 (diff) | |
8029101: PPC64 (part 211): ordering of Independent Reads of Independent Writes
Reviewed-by: dholmes, kvn
Contributed-by: martin.doerr@sap.com
Diffstat (limited to 'src/share/vm/utilities')
| -rw-r--r-- | src/share/vm/utilities/globalDefinitions.hpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/share/vm/utilities/globalDefinitions.hpp b/src/share/vm/utilities/globalDefinitions.hpp index e522a98d7..6461d8303 100644 --- a/src/share/vm/utilities/globalDefinitions.hpp +++ b/src/share/vm/utilities/globalDefinitions.hpp @@ -398,6 +398,17 @@ const uint64_t KlassEncodingMetaspaceMax = (uint64_t(max_juint) + 1) << LogKlass #define PLATFORM_NATIVE_STACK_WALKING_SUPPORTED 1 #endif +// To assure the IRIW property on processors that are not multiple copy +// atomic, sync instructions must be issued between volatile reads to +// assure their ordering, instead of after volatile stores. +// (See "A Tutorial Introduction to the ARM and POWER Relaxed Memory Models" +// by Luc Maranget, Susmit Sarkar and Peter Sewell, INRIA/Cambridge) +#ifdef CPU_NOT_MULTIPLE_COPY_ATOMIC +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = true; +#else +const bool support_IRIW_for_not_multiple_copy_atomic_cpu = false; +#endif + // The byte alignment to be used by Arena::Amalloc. See bugid 4169348. // Note: this value must be a power of 2 |