aboutsummaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
authorkvn <none@none>2012-09-19 16:50:26 -0700
committerkvn <none@none>2012-09-19 16:50:26 -0700
commit9c4aa71c8a7562754876d0ec6bdfaa9f6e54e0c9 (patch)
tree3357b4a3d2e2d7e56744ea6dac5b0afae1849913 /src/cpu
parent227d8c51ed3eb5ad784ce40d32e7480ef95423b2 (diff)
7199010: incorrect vector alignment
Summary: Fixed vectors alignment when several arrays are accessed in one loop. Reviewed-by: roland, twisti
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/x86/vm/vm_version_x86.cpp21
1 files changed, 14 insertions, 7 deletions
diff --git a/src/cpu/x86/vm/vm_version_x86.cpp b/src/cpu/x86/vm/vm_version_x86.cpp
index 12f3f2584..a5de1eefb 100644
--- a/src/cpu/x86/vm/vm_version_x86.cpp
+++ b/src/cpu/x86/vm/vm_version_x86.cpp
@@ -562,10 +562,10 @@ void VM_Version::get_processor_features() {
AllocatePrefetchInstr = 3;
}
// On family 15h processors use XMM and UnalignedLoadStores for Array Copy
- if( supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
+ if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
UseXMMForArrayCopy = true;
}
- if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
+ if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
UseUnalignedLoadStores = true;
}
}
@@ -612,16 +612,16 @@ void VM_Version::get_processor_features() {
MaxLoopPad = 11;
}
#endif // COMPILER2
- if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
+ if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
}
- if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
- if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
+ if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
+ if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
}
}
- if( supports_sse4_2() && UseSSE >= 4 ) {
- if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
+ if (supports_sse4_2() && UseSSE >= 4) {
+ if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
UseSSE42Intrinsics = true;
}
}
@@ -638,6 +638,13 @@ void VM_Version::get_processor_features() {
FLAG_SET_DEFAULT(UsePopCountInstruction, false);
}
+#ifdef COMPILER2
+ if (FLAG_IS_DEFAULT(AlignVector)) {
+ // Modern processors allow misaligned memory operations for vectors.
+ AlignVector = !UseUnalignedLoadStores;
+ }
+#endif // COMPILER2
+
assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");