7201026: add vector for shift count

Summary: Add generation of vectors for scalar shift count.
Reviewed-by: roland, twisti, dlong

2 files changed, 59 insertions, 35 deletions

diff --git a/src/cpu/sparc/vm/sparc.ad b/src/cpu/sparc/vm/sparc.ad
index f7040f54e..f6e7d03b6 100644
--- a/src/cpu/sparc/vm/sparc.ad
+++ b/src/cpu/sparc/vm/sparc.ad
@@ -1870,6 +1870,11 @@ const int Matcher::vector_ideal_reg(int size) {
   return Op_RegD;
 }
 
+const int Matcher::vector_shift_count_ideal_reg(int size) {
+  fatal("vector shift is not supported");
+  return Node::NotAMachineReg;
+}
+
 // Limits on vector size (number of elements) loaded into vector.
 const int Matcher::max_vector_size(const BasicType bt) {
   assert(is_java_primitive(bt), "only primitive type vectors");
diff --git a/src/cpu/x86/vm/x86.ad b/src/cpu/x86/vm/x86.ad
index c3831006b..a2cf6f794 100644
--- a/src/cpu/x86/vm/x86.ad
+++ b/src/cpu/x86/vm/x86.ad
@@ -571,6 +571,11 @@ const int Matcher::vector_ideal_reg(int size) {
   return 0;
 }
 
+// Only lowest bits of xmm reg are used for vector shift count.
+const int Matcher::vector_shift_count_ideal_reg(int size) {
+  return Op_VecS;
+}
+
 // x86 supports misaligned vectors store/load.
 const bool Matcher::misaligned_vectors_ok() {
   return !AlignVector; // can be changed by flag
@@ -3758,10 +3763,24 @@ instruct vdiv4D_mem(vecY dst, vecY src, memory mem) %{
   ins_pipe( pipe_slow );
 %}
 
+// ------------------------------ Shift ---------------------------------------
+
+// Left and right shift count vectors are the same on x86
+// (only lowest bits of xmm reg are used for count).
+instruct vshiftcnt(vecS dst, rRegI cnt) %{
+  match(Set dst (LShiftCntV cnt));
+  match(Set dst (RShiftCntV cnt));
+  format %{ "movd    $dst,$cnt\t! load shift count" %}
+  ins_encode %{
+    __ movdl($dst$$XMMRegister, $cnt$$Register);
+  %}
+  ins_pipe( pipe_slow );
+%}
+
 // ------------------------------ LeftShift -----------------------------------
 
 // Shorts/Chars vector left shift
-instruct vsll2S(vecS dst, regF shift) %{
+instruct vsll2S(vecS dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (LShiftVS dst shift));
   format %{ "psllw   $dst,$shift\t! left shift packed2S" %}
@@ -3781,7 +3800,7 @@ instruct vsll2S_imm(vecS dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll2S_reg(vecS dst, vecS src, regF shift) %{
+instruct vsll2S_reg(vecS dst, vecS src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   match(Set dst (LShiftVS src shift));
   format %{ "vpsllw  $dst,$src,$shift\t! left shift packed2S" %}
@@ -3803,7 +3822,7 @@ instruct vsll2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll4S(vecD dst, regF shift) %{
+instruct vsll4S(vecD dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (LShiftVS dst shift));
   format %{ "psllw   $dst,$shift\t! left shift packed4S" %}
@@ -3823,7 +3842,7 @@ instruct vsll4S_imm(vecD dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll4S_reg(vecD dst, vecD src, regF shift) %{
+instruct vsll4S_reg(vecD dst, vecD src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   match(Set dst (LShiftVS src shift));
   format %{ "vpsllw  $dst,$src,$shift\t! left shift packed4S" %}
@@ -3845,7 +3864,7 @@ instruct vsll4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll8S(vecX dst, regF shift) %{
+instruct vsll8S(vecX dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 8);
   match(Set dst (LShiftVS dst shift));
   format %{ "psllw   $dst,$shift\t! left shift packed8S" %}
@@ -3865,7 +3884,7 @@ instruct vsll8S_imm(vecX dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll8S_reg(vecX dst, vecX src, regF shift) %{
+instruct vsll8S_reg(vecX dst, vecX src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
   match(Set dst (LShiftVS src shift));
   format %{ "vpsllw  $dst,$src,$shift\t! left shift packed8S" %}
@@ -3887,7 +3906,7 @@ instruct vsll8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll16S_reg(vecY dst, vecY src, regF shift) %{
+instruct vsll16S_reg(vecY dst, vecY src, vecS shift) %{
   predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
   match(Set dst (LShiftVS src shift));
   format %{ "vpsllw  $dst,$src,$shift\t! left shift packed16S" %}
@@ -3910,7 +3929,7 @@ instruct vsll16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
 %}
 
 // Integers vector left shift
-instruct vsll2I(vecD dst, regF shift) %{
+instruct vsll2I(vecD dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (LShiftVI dst shift));
   format %{ "pslld   $dst,$shift\t! left shift packed2I" %}
@@ -3930,7 +3949,7 @@ instruct vsll2I_imm(vecD dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll2I_reg(vecD dst, vecD src, regF shift) %{
+instruct vsll2I_reg(vecD dst, vecD src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   match(Set dst (LShiftVI src shift));
   format %{ "vpslld  $dst,$src,$shift\t! left shift packed2I" %}
@@ -3952,7 +3971,7 @@ instruct vsll2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll4I(vecX dst, regF shift) %{
+instruct vsll4I(vecX dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (LShiftVI dst shift));
   format %{ "pslld   $dst,$shift\t! left shift packed4I" %}
@@ -3972,7 +3991,7 @@ instruct vsll4I_imm(vecX dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll4I_reg(vecX dst, vecX src, regF shift) %{
+instruct vsll4I_reg(vecX dst, vecX src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   match(Set dst (LShiftVI src shift));
   format %{ "vpslld  $dst,$src,$shift\t! left shift packed4I" %}
@@ -3994,7 +4013,7 @@ instruct vsll4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll8I_reg(vecY dst, vecY src, regF shift) %{
+instruct vsll8I_reg(vecY dst, vecY src, vecS shift) %{
   predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
   match(Set dst (LShiftVI src shift));
   format %{ "vpslld  $dst,$src,$shift\t! left shift packed8I" %}
@@ -4017,7 +4036,7 @@ instruct vsll8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
 %}
 
 // Longs vector left shift
-instruct vsll2L(vecX dst, regF shift) %{
+instruct vsll2L(vecX dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (LShiftVL dst shift));
   format %{ "psllq   $dst,$shift\t! left shift packed2L" %}
@@ -4037,7 +4056,7 @@ instruct vsll2L_imm(vecX dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll2L_reg(vecX dst, vecX src, regF shift) %{
+instruct vsll2L_reg(vecX dst, vecX src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   match(Set dst (LShiftVL src shift));
   format %{ "vpsllq  $dst,$src,$shift\t! left shift packed2L" %}
@@ -4059,7 +4078,7 @@ instruct vsll2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsll4L_reg(vecY dst, vecY src, regF shift) %{
+instruct vsll4L_reg(vecY dst, vecY src, vecS shift) %{
   predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
   match(Set dst (LShiftVL src shift));
   format %{ "vpsllq  $dst,$src,$shift\t! left shift packed4L" %}
@@ -4088,7 +4107,7 @@ instruct vsll4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
 // sign extension before a shift.
 
 // Integers vector logical right shift
-instruct vsrl2I(vecD dst, regF shift) %{
+instruct vsrl2I(vecD dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (URShiftVI dst shift));
   format %{ "psrld   $dst,$shift\t! logical right shift packed2I" %}
@@ -4108,7 +4127,7 @@ instruct vsrl2I_imm(vecD dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsrl2I_reg(vecD dst, vecD src, regF shift) %{
+instruct vsrl2I_reg(vecD dst, vecD src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   match(Set dst (URShiftVI src shift));
   format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed2I" %}
@@ -4130,7 +4149,7 @@ instruct vsrl2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsrl4I(vecX dst, regF shift) %{
+instruct vsrl4I(vecX dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (URShiftVI dst shift));
   format %{ "psrld   $dst,$shift\t! logical right shift packed4I" %}
@@ -4150,7 +4169,7 @@ instruct vsrl4I_imm(vecX dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsrl4I_reg(vecX dst, vecX src, regF shift) %{
+instruct vsrl4I_reg(vecX dst, vecX src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   match(Set dst (URShiftVI src shift));
   format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed4I" %}
@@ -4172,7 +4191,7 @@ instruct vsrl4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsrl8I_reg(vecY dst, vecY src, regF shift) %{
+instruct vsrl8I_reg(vecY dst, vecY src, vecS shift) %{
   predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
   match(Set dst (URShiftVI src shift));
   format %{ "vpsrld  $dst,$src,$shift\t! logical right shift packed8I" %}
@@ -4195,7 +4214,7 @@ instruct vsrl8I_reg_imm(vecY dst, vecY src, immI8 shift) %{
 %}
 
 // Longs vector logical right shift
-instruct vsrl2L(vecX dst, regF shift) %{
+instruct vsrl2L(vecX dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (URShiftVL dst shift));
   format %{ "psrlq   $dst,$shift\t! logical right shift packed2L" %}
@@ -4215,7 +4234,7 @@ instruct vsrl2L_imm(vecX dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsrl2L_reg(vecX dst, vecX src, regF shift) %{
+instruct vsrl2L_reg(vecX dst, vecX src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   match(Set dst (URShiftVL src shift));
   format %{ "vpsrlq  $dst,$src,$shift\t! logical right shift packed2L" %}
@@ -4237,7 +4256,7 @@ instruct vsrl2L_reg_imm(vecX dst, vecX src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsrl4L_reg(vecY dst, vecY src, regF shift) %{
+instruct vsrl4L_reg(vecY dst, vecY src, vecS shift) %{
   predicate(UseAVX > 1 && n->as_Vector()->length() == 4);
   match(Set dst (URShiftVL src shift));
   format %{ "vpsrlq  $dst,$src,$shift\t! logical right shift packed4L" %}
@@ -4262,7 +4281,7 @@ instruct vsrl4L_reg_imm(vecY dst, vecY src, immI8 shift) %{
 // ------------------- ArithmeticRightShift -----------------------------------
 
 // Shorts/Chars vector arithmetic right shift
-instruct vsra2S(vecS dst, regF shift) %{
+instruct vsra2S(vecS dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (RShiftVS dst shift));
   format %{ "psraw   $dst,$shift\t! arithmetic right shift packed2S" %}
@@ -4282,7 +4301,7 @@ instruct vsra2S_imm(vecS dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra2S_reg(vecS dst, vecS src, regF shift) %{
+instruct vsra2S_reg(vecS dst, vecS src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   match(Set dst (RShiftVS src shift));
   format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed2S" %}
@@ -4304,7 +4323,7 @@ instruct vsra2S_reg_imm(vecS dst, vecS src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra4S(vecD dst, regF shift) %{
+instruct vsra4S(vecD dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (RShiftVS dst shift));
   format %{ "psraw   $dst,$shift\t! arithmetic right shift packed4S" %}
@@ -4324,7 +4343,7 @@ instruct vsra4S_imm(vecD dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra4S_reg(vecD dst, vecD src, regF shift) %{
+instruct vsra4S_reg(vecD dst, vecD src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   match(Set dst (RShiftVS src shift));
   format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed4S" %}
@@ -4346,7 +4365,7 @@ instruct vsra4S_reg_imm(vecD dst, vecD src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra8S(vecX dst, regF shift) %{
+instruct vsra8S(vecX dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 8);
   match(Set dst (RShiftVS dst shift));
   format %{ "psraw   $dst,$shift\t! arithmetic right shift packed8S" %}
@@ -4366,7 +4385,7 @@ instruct vsra8S_imm(vecX dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra8S_reg(vecX dst, vecX src, regF shift) %{
+instruct vsra8S_reg(vecX dst, vecX src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 8);
   match(Set dst (RShiftVS src shift));
   format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed8S" %}
@@ -4388,7 +4407,7 @@ instruct vsra8S_reg_imm(vecX dst, vecX src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra16S_reg(vecY dst, vecY src, regF shift) %{
+instruct vsra16S_reg(vecY dst, vecY src, vecS shift) %{
   predicate(UseAVX > 1 && n->as_Vector()->length() == 16);
   match(Set dst (RShiftVS src shift));
   format %{ "vpsraw  $dst,$src,$shift\t! arithmetic right shift packed16S" %}
@@ -4411,7 +4430,7 @@ instruct vsra16S_reg_imm(vecY dst, vecY src, immI8 shift) %{
 %}
 
 // Integers vector arithmetic right shift
-instruct vsra2I(vecD dst, regF shift) %{
+instruct vsra2I(vecD dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 2);
   match(Set dst (RShiftVI dst shift));
   format %{ "psrad   $dst,$shift\t! arithmetic right shift packed2I" %}
@@ -4431,7 +4450,7 @@ instruct vsra2I_imm(vecD dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra2I_reg(vecD dst, vecD src, regF shift) %{
+instruct vsra2I_reg(vecD dst, vecD src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 2);
   match(Set dst (RShiftVI src shift));
   format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed2I" %}
@@ -4453,7 +4472,7 @@ instruct vsra2I_reg_imm(vecD dst, vecD src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra4I(vecX dst, regF shift) %{
+instruct vsra4I(vecX dst, vecS shift) %{
   predicate(n->as_Vector()->length() == 4);
   match(Set dst (RShiftVI dst shift));
   format %{ "psrad   $dst,$shift\t! arithmetic right shift packed4I" %}
@@ -4473,7 +4492,7 @@ instruct vsra4I_imm(vecX dst, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra4I_reg(vecX dst, vecX src, regF shift) %{
+instruct vsra4I_reg(vecX dst, vecX src, vecS shift) %{
   predicate(UseAVX > 0 && n->as_Vector()->length() == 4);
   match(Set dst (RShiftVI src shift));
   format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed4I" %}
@@ -4495,7 +4514,7 @@ instruct vsra4I_reg_imm(vecX dst, vecX src, immI8 shift) %{
   ins_pipe( pipe_slow );
 %}
 
-instruct vsra8I_reg(vecY dst, vecY src, regF shift) %{
+instruct vsra8I_reg(vecY dst, vecY src, vecS shift) %{
   predicate(UseAVX > 1 && n->as_Vector()->length() == 8);
   match(Set dst (RShiftVI src shift));
   format %{ "vpsrad  $dst,$src,$shift\t! arithmetic right shift packed8I" %}