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authorEdward Nevill edward.nevill@linaro.org <Edward Nevill edward.nevill@linaro.org>2014-07-07 16:24:51 +0100
committerEdward Nevill edward.nevill@linaro.org <Edward Nevill edward.nevill@linaro.org>2014-07-07 16:24:51 +0100
commit914f9f34594404ad91c05e9f8819e0b2187eb459 (patch)
tree7c2100895a682c3ac8e7a41acedf89334c3a43b0
parent152c21f89be01a541bbc1ce5bb9da2be4e8ff4c2 (diff)
Add support for MathExact intrinsics
-rw-r--r--src/cpu/aarch64/vm/aarch64.ad133
-rw-r--r--test/compiler/intrinsics/mathexact/sanity/IntrinsicBase.java4
-rw-r--r--test/testlibrary/com/oracle/java/testlibrary/Platform.java4
3 files changed, 139 insertions, 2 deletions
diff --git a/src/cpu/aarch64/vm/aarch64.ad b/src/cpu/aarch64/vm/aarch64.ad
index 3a912e104..12367469d 100644
--- a/src/cpu/aarch64/vm/aarch64.ad
+++ b/src/cpu/aarch64/vm/aarch64.ad
@@ -10470,6 +10470,139 @@ instruct clearArray_reg_reg(iRegL_R11 cnt, iRegP_R10 base, Universe dummy, rFlag
%}
// ============================================================================
+// Overflow Math Instructions
+
+instruct overflowAddI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
+%{
+ match(Set cr (OverflowAddI op1 op2));
+
+ format %{ "cmnw $op1, $op2\t# overflow check int" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmnw($op1$$Register, $op2$$Register);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowAddI_reg_imm(rFlagsReg cr, iRegI op1, immIAddSub op2)
+%{
+ match(Set cr (OverflowAddI op1 op2));
+
+ format %{ "cmnw $op1, $op2\t# overflow check int" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmnw($op1$$Register, $op2$$constant);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowAddL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
+%{
+ match(Set cr (OverflowAddL op1 op2));
+
+ format %{ "cmn $op1, $op2\t# overflow check long" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmn($op1$$Register, $op2$$Register);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowAddL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
+%{
+ match(Set cr (OverflowAddL op1 op2));
+
+ format %{ "cmn $op1, $op2\t# overflow check long" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmn($op1$$Register, $op2$$constant);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowSubI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
+%{
+ match(Set cr (OverflowSubI op1 op2));
+
+ format %{ "cmpw $op1, $op2\t# overflow check int" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmpw($op1$$Register, $op2$$Register);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowSubI_reg_imm(rFlagsReg cr, iRegI op1, immIAddSub op2)
+%{
+ match(Set cr (OverflowSubI op1 op2));
+
+ format %{ "cmpw $op1, $op2\t# overflow check int" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmpw($op1$$Register, $op2$$constant);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowSubL_reg_reg(rFlagsReg cr, iRegL op1, iRegL op2)
+%{
+ match(Set cr (OverflowSubL op1 op2));
+
+ format %{ "cmp $op1, $op2\t# overflow check long" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmp($op1$$Register, $op2$$Register);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowSubL_reg_imm(rFlagsReg cr, iRegL op1, immLAddSub op2)
+%{
+ match(Set cr (OverflowSubL op1 op2));
+
+ format %{ "cmp $op1, $op2\t# overflow check long" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmp($op1$$Register, $op2$$constant);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowNegI_reg(rFlagsReg cr, immI0 zero, iRegI op2)
+%{
+ match(Set cr (OverflowSubI zero op2));
+
+ format %{ "cmpw zr, $op2\t# overflow check int" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmpw(zr, $op2$$Register);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+instruct overflowNegL_reg(rFlagsReg cr, immI0 zero, iRegL op2)
+%{
+ match(Set cr (OverflowSubL zero op2));
+
+ format %{ "cmp zr, $op2\t# overflow check long" %}
+ ins_cost(INSN_COST);
+ ins_encode %{
+ __ cmp(zr, $op2$$Register);
+ %}
+
+ ins_pipe(pipe_class_default);
+%}
+
+// ============================================================================
// Compare Instructions
instruct compI_reg_reg(rFlagsReg cr, iRegI op1, iRegI op2)
diff --git a/test/compiler/intrinsics/mathexact/sanity/IntrinsicBase.java b/test/compiler/intrinsics/mathexact/sanity/IntrinsicBase.java
index cecd6ce2d..337007dd7 100644
--- a/test/compiler/intrinsics/mathexact/sanity/IntrinsicBase.java
+++ b/test/compiler/intrinsics/mathexact/sanity/IntrinsicBase.java
@@ -128,7 +128,7 @@ public abstract class IntrinsicBase extends CompilerWhiteBoxTest {
@Override
protected boolean isIntrinsicSupported() {
- return isServerVM() && Boolean.valueOf(useMathExactIntrinsics) && (Platform.isX86() || Platform.isX64());
+ return isServerVM() && Boolean.valueOf(useMathExactIntrinsics) && (Platform.isX86() || Platform.isX64() || Platform.isAArch64());
}
@Override
@@ -144,7 +144,7 @@ public abstract class IntrinsicBase extends CompilerWhiteBoxTest {
@Override
protected boolean isIntrinsicSupported() {
- return isServerVM() && Boolean.valueOf(useMathExactIntrinsics) && Platform.isX64();
+ return isServerVM() && Boolean.valueOf(useMathExactIntrinsics) && (Platform.isX64() || Platform.isAArch64());
}
@Override
diff --git a/test/testlibrary/com/oracle/java/testlibrary/Platform.java b/test/testlibrary/com/oracle/java/testlibrary/Platform.java
index fa4b36361..9bce59585 100644
--- a/test/testlibrary/com/oracle/java/testlibrary/Platform.java
+++ b/test/testlibrary/com/oracle/java/testlibrary/Platform.java
@@ -113,6 +113,10 @@ public class Platform {
return (isArch("amd64") || isArch("x86_64"));
}
+ public static boolean isAArch64() {
+ return isArch("aarch64");
+ }
+
private static boolean isArch(String archname) {
return osArch.toLowerCase().startsWith(archname.toLowerCase());
}