removed lots of redundant code

deleted lots of methdos which were only needed for x86

merely ifdeffed out MacroAssembler methods in asembler-aarch64.hpp
which were not defined as some of them represent abstractions which we
may well need later

18 files changed, 96 insertions, 743 deletions

diff --git a/src/cpu/aarch64/vm/assembler_aarch64.hpp b/src/cpu/aarch64/vm/assembler_aarch64.hpp
index 9a7c4ab7a..08a653624 100644
--- a/src/cpu/aarch64/vm/assembler_aarch64.hpp
+++ b/src/cpu/aarch64/vm/assembler_aarch64.hpp
@@ -2390,6 +2390,8 @@ public:
   void store_check_part_1(Register obj);
   void store_check_part_2(Register obj);
 
+  // currently unimplemented
+#if 0
   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
   void c2bool(Register x);
 
@@ -2399,20 +2401,26 @@ public:
   void movbool(Address dst, bool boolconst);
   void movbool(Address dst, Register src);
   void testbool(Register dst);
+#endif
 
   // oop manipulations
   void load_klass(Register dst, Register src);
   void store_klass(Register dst, Register src);
 
   void load_heap_oop(Register dst, Address src);
+
   void load_heap_oop_not_null(Register dst, Address src);
   void store_heap_oop(Address dst, Register src);
 
+  // currently unimplemented
   // Used for storing NULL. All other oop constants should be
   // stored using routines that take a jobject.
   void store_heap_oop_null(Address dst);
 
+  // currently unimplemented
+#if 0
   void load_prototype_header(Register dst, Register src);
+#endif
 
   void store_klass_gap(Register dst, Register src);
 
@@ -2429,10 +2437,13 @@ public:
   void encode_heap_oop_not_null(Register dst, Register src);
   void decode_heap_oop_not_null(Register dst, Register src);
 
+  // currently unimplemented
+#if 0
   void set_narrow_oop(Register dst, jobject obj);
   void set_narrow_oop(Address dst, jobject obj);
   void cmp_narrow_oop(Register dst, jobject obj);
   void cmp_narrow_oop(Address dst, jobject obj);
+#endif
 
   // if heap base register is used - reinit it with the correct value
   void reinit_heapbase();
@@ -2449,8 +2460,13 @@ public:
   // returns idivq instruction offset for implicit exception handling
   int corrected_idivq(Register reg);
 
+  // currently unimplemented
+#if 0
   void int3();
+#endif
 
+  // currently unimplemented
+#if 0
   // Long operation macros for a 32bit cpu
   // Long negation for Java
   void lneg(Register hi, Register lo);
@@ -2477,7 +2493,10 @@ public:
 
   // Division by power of 2, rounding towards 0
   void division_with_shift(Register reg, int shift_value);
+#endif
 
+  // unimpelements
+#if 0
   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
   //
   // CF (corresponds to C0) if x < y
@@ -2526,17 +2545,26 @@ public:
 
   void push_FPU_state();
   void pop_FPU_state();
+#endif
 
   void push_CPU_state();
+  // unimplemented
+#if 0
   void pop_CPU_state();
+#endif
 
   // Round up to a power of two
   void round_to(Register reg, int modulus);
 
+  // unimplemented
+#if 0
   // Callee saved registers handling
   void push_callee_saved_registers();
   void pop_callee_saved_registers();
+#endif
 
+  // unimplemented
+#if 0
   // allocation
   void eden_allocate(
     Register obj,                      // result: pointer to object after successful allocation
@@ -2554,6 +2582,7 @@ public:
     Label&   slow_case                 // continuation point if fast allocation fails
   );
   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
+#endif
   void incr_allocated_bytes(Register thread,
                             Register var_size_in_bytes, int con_size_in_bytes,
                             Register t1 = noreg);
@@ -2606,6 +2635,8 @@ public:
                            Register temp_reg,
                            Label& L_success);
 
+  // unimplemented
+#if 0
   // method handles (JSR 292)
   void check_method_handle_type(Register mtype_reg, Register mh_reg,
                                 Register temp_reg,
@@ -2613,17 +2644,24 @@ public:
   void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
                                   Register temp_reg);
   void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
+#endif
   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 
 
   //----
+#if 0
+  // method handles (JSR 292)
   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
+#endif
 
   // Debugging
 
   // only if +VerifyOops
   void verify_oop(Register reg, const char* s = "broken oop");
+  // unimplemented
+#if 0
   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
+#endif
 
 // TODO: verify method and klass metadata (compare against vptr?)
   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
@@ -2643,7 +2681,10 @@ public:
 
   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 
+  // unimplemented
+#if 0
   void os_breakpoint();
+#endif
 
   void untested()                                { stop("untested"); }
 
@@ -2651,7 +2692,10 @@ public:
 
   void should_not_reach_here()                   { stop("should not reach here"); }
 
+  // unimplemented
+#if 0
   void print_CPU_state();
+#endif
 
   // Stack overflow checking
   void bang_stack_with_offset(int offset) {
@@ -2661,9 +2705,12 @@ public:
     ldr(zr, Address(sp, rscratch2));
   }
 
+  // unimplemented
+#if 0
   // Writes to stack successive pages until offset reached to check for
   // stack overflow + shadow pages.  Also, clobbers tmp
   void bang_stack_size(Register size, Register tmp);
+#endif
 
   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
                                                 Register tmp,
@@ -2672,6 +2719,8 @@ public:
   // Support for serializing memory accesses between threads
   void serialize_memory(Register thread, Register tmp);
 
+  // unimplemented
+#if 0
   void verify_tlab();
 
   // Biased locking support
@@ -2695,30 +2744,38 @@ public:
 
 
   Condition negate_condition(Condition cond);
+#endif
 
   // Arithmetics
 
 
   void addptr(Address dst, int32_t src) { Unimplemented(); }
+  // unimplemented
+#if 0
   void addptr(Address dst, Register src);
+#endif
 
   void addptr(Register dst, Address src) { Unimplemented(); }
+  // unimplemented
+#if 0
   void addptr(Register dst, int32_t src);
   void addptr(Register dst, Register src);
+#endif
   void addptr(Register dst, RegisterOrConstant src) { Unimplemented(); }
 
+  // unimplemented
+#if 0
   void andptr(Register dst, int32_t src);
+#endif
   void andptr(Register src1, Register src2) { Unimplemented(); }
 
+  // unimplemented
+#if 0
   // renamed to drag out the casting of address to int32_t/intptr_t
   void cmp32(Register src1, int32_t imm);
 
   void cmp32(Register src1, Address src2);
-
-#ifndef _LP64
-  void cmpoop(Address dst, jobject obj);
-  void cmpoop(Register dst, jobject obj);
-#endif // _LP64
+#endif
 
   void cmpptr(Register src1, Register src2) { Unimplemented(); }
   void cmpptr(Register src1, Address src2);
@@ -2737,10 +2794,16 @@ public:
 
   void notptr(Register dst) { Unimplemented(); }
 
+  // unimplemented
+#if 0
   void shlptr(Register dst, int32_t shift);
+#endif
   void shlptr(Register dst) { Unimplemented(); }
 
+  // unimplemented
+#if 0
   void shrptr(Register dst, int32_t shift);
+#endif
   void shrptr(Register dst) { Unimplemented(); }
 
   void sarptr(Register dst) { Unimplemented(); }
@@ -2749,10 +2812,13 @@ public:
   void subptr(Address dst, int32_t src) { Unimplemented(); }
 
   void subptr(Register dst, Address src) { Unimplemented(); }
+  // unimplemented
+#if 0
   void subptr(Register dst, int32_t src);
   // Force generation of a 4 byte immediate value even if it fits into 8bit
   void subptr_imm32(Register dst, int32_t src);
   void subptr(Register dst, Register src);
+#endif
   void subptr(Register dst, RegisterOrConstant src) { Unimplemented(); }
 
   void sbbptr(Address dst, int32_t src) { Unimplemented(); }
@@ -2765,6 +2831,7 @@ public:
 
 
 
+  // unimplemented
 #if 0
 
   // Perhaps we should implement this one
@@ -2789,11 +2856,14 @@ public:
 
   // Jumps
 
+  // unimplemented
+#if 0
   // NOTE: these jumps tranfer to the effective address of dst NOT
   // the address contained by dst. This is because this is more natural
   // for jumps/calls.
   void jump(Address dst);
   void jump_cc(Condition cc, Address dst);
+#endif
 
   // Floating
 
@@ -2810,13 +2880,14 @@ public:
 
   void fmul_s(Address src)        { Unimplemented(); }
 
-  void ldmxcsr(Address src) { Unimplemented(); }
-
+  // unimplemented
+#if 0
   // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
   // all corner cases and may result in NaN and require fallback to a
   // runtime call.
   void fast_pow();
   void fast_exp();
+#endif
 
   // computes exp(x). Fallback to runtime call included.
   void exp_with_fallback(int num_fpu_regs_in_use) { Unimplemented(); }
@@ -2827,19 +2898,23 @@ public:
 
   // Data
 
+  // unimplemented
+#if 0
   void pushoop(jobject obj);
+#endif
 
   // sign extend as need a l to ptr sized element
   void movl2ptr(Register dst, Address src) { Unimplemented(); }
   void movl2ptr(Register dst, Register src) { Unimplemented(); }
 
+  // unimplemented
+#if 0
   // C2 compiled method's prolog code.
   void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b);
+#endif
 
 #undef VIRTUAL
 
-  // MacroAssembler routines found definitely to be needed
-
   // Stack push and pop individual 64 bit registers
   void push(Register src);
   void pop(Register dst);
diff --git a/src/cpu/aarch64/vm/bytes_aarch64.hpp b/src/cpu/aarch64/vm/bytes_aarch64.hpp
index d8ca7c824..063464559 100644
--- a/src/cpu/aarch64/vm/bytes_aarch64.hpp
+++ b/src/cpu/aarch64/vm/bytes_aarch64.hpp
@@ -66,21 +66,9 @@ class Bytes: AllStatic {
 
 
 // The following header contains the implementations of swap_u2, swap_u4, and swap_u8[_base]
-#ifdef TARGET_OS_ARCH_linux_x86
-# include "bytes_linux_x86.inline.hpp"
-#endif
+
 #ifdef TARGET_OS_ARCH_linux_aarch64
 # include "bytes_linux_aarch64.inline.hpp"
 #endif
-#ifdef TARGET_OS_ARCH_solaris_x86
-# include "bytes_solaris_x86.inline.hpp"
-#endif
-#ifdef TARGET_OS_ARCH_windows_x86
-# include "bytes_windows_x86.inline.hpp"
-#endif
-#ifdef TARGET_OS_ARCH_bsd_x86
-# include "bytes_bsd_x86.inline.hpp"
-#endif
-
 
 #endif // CPU_AARCH64_VM_BYTES_AARCH64_HPP
diff --git a/src/cpu/aarch64/vm/copy_aarch64.hpp b/src/cpu/aarch64/vm/copy_aarch64.hpp
index 68eaee4b2..31bd14da8 100644
--- a/src/cpu/aarch64/vm/copy_aarch64.hpp
+++ b/src/cpu/aarch64/vm/copy_aarch64.hpp
@@ -31,18 +31,6 @@
 #ifdef TARGET_OS_ARCH_linux_aarch64
 # include "copy_linux_aarch64.inline.hpp"
 #endif
-#ifdef TARGET_OS_ARCH_linux_x86
-# include "copy_linux_x86.inline.hpp"
-#endif
-#ifdef TARGET_OS_ARCH_solaris_x86
-# include "copy_solaris_x86.inline.hpp"
-#endif
-#ifdef TARGET_OS_ARCH_windows_x86
-# include "copy_windows_x86.inline.hpp"
-#endif
-#ifdef TARGET_OS_ARCH_bsd_x86
-# include "copy_bsd_x86.inline.hpp"
-#endif
 
 
 static void pd_fill_to_words(HeapWord* tohw, size_t count, juint value) {
diff --git a/src/cpu/aarch64/vm/depChecker_aarch64.cpp b/src/cpu/aarch64/vm/depChecker_aarch64.cpp
index be90089b0..c97ef29ec 100644
--- a/src/cpu/aarch64/vm/depChecker_aarch64.cpp
+++ b/src/cpu/aarch64/vm/depChecker_aarch64.cpp
@@ -26,4 +26,4 @@
 #include "compiler/disassembler.hpp"
 #include "depChecker_aarch64.hpp"
 
-// Nothing to do on i486
+// Nothing to do on aarch64
diff --git a/src/cpu/aarch64/vm/depChecker_aarch64.hpp b/src/cpu/aarch64/vm/depChecker_aarch64.hpp
index 33d881749..7e49305d1 100644
--- a/src/cpu/aarch64/vm/depChecker_aarch64.hpp
+++ b/src/cpu/aarch64/vm/depChecker_aarch64.hpp
@@ -25,6 +25,6 @@
 #ifndef CPU_AARCH64_VM_DEPCHECKER_AARCH64_HPP
 #define CPU_AARCH64_VM_DEPCHECKER_AARCH64_HPP
 
-// Nothing to do on i486
+// Nothing to do on aarch64
 
 #endif // CPU_AARCH64_VM_DEPCHECKER_AARCH64_HPP
diff --git a/src/cpu/aarch64/vm/globals_aarch64.hpp b/src/cpu/aarch64/vm/globals_aarch64.hpp
index 07ea8a7d3..fcf6ebd78 100644
--- a/src/cpu/aarch64/vm/globals_aarch64.hpp
+++ b/src/cpu/aarch64/vm/globals_aarch64.hpp
@@ -64,11 +64,7 @@ define_pd_global(intx, PreInflateSpin,           10);
 define_pd_global(bool, RewriteBytecodes,     true);
 define_pd_global(bool, RewriteFrequentPairs, false);
 
-#ifdef _ALLBSD_SOURCE
-define_pd_global(bool, UseMembar,            true);
-#else
 define_pd_global(bool, UseMembar,            false);
-#endif
 
 // GC Ergo Flags
 define_pd_global(intx, CMSYoungGenPerWorker, 64*M);  // default max size of CMS young gen, per GC worker thread
diff --git a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp
index 65f7be6cb..36c4e48bd 100644
--- a/src/cpu/aarch64/vm/interp_masm_aarch64.cpp
+++ b/src/cpu/aarch64/vm/interp_masm_aarch64.cpp
@@ -39,15 +39,6 @@
 #ifdef TARGET_OS_FAMILY_linux
 # include "thread_linux.inline.hpp"
 #endif
-#ifdef TARGET_OS_FAMILY_solaris
-# include "thread_solaris.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_windows
-# include "thread_windows.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_bsd
-# include "thread_bsd.inline.hpp"
-#endif
 
 
 // Implementation of InterpreterMacroAssembler
@@ -172,7 +163,7 @@ void InterpreterMacroAssembler::load_resolved_reference_at_index(
 //      Rsub_klass: subklass
 //
 // Kills:
-//      rcx, rdi
+//      r2, r5
 void InterpreterMacroAssembler::gen_subtype_check(Register Rsub_klass,
                                                   Label& ok_is_subtype) {
   assert(Rsub_klass != r0, "r0 holds superklass");
@@ -432,7 +423,7 @@ void InterpreterMacroAssembler::remove_activation(
   // objects has been unlocked)
   bind(unlocked);
 
-  // rax: Might contain return value
+  // r0: Might contain return value
 
   // Check that all monitors are unlocked
   {
@@ -519,7 +510,7 @@ void InterpreterMacroAssembler::remove_activation(
 //      c_rarg1: BasicObjectLock to be used for locking
 //
 // Kills:
-//      rax
+//      r0
 //      c_rarg0, c_rarg1, c_rarg2, c_rarg3, .. (param regs)
 //      rscratch1, rscratch2 (scratch regs)
 void InterpreterMacroAssembler::lock_object(Register lock_reg)
@@ -619,7 +610,7 @@ void InterpreterMacroAssembler::lock_object(Register lock_reg)
 //      c_rarg1: BasicObjectLock for lock
 //
 // Kills:
-//      rax
+//      r0
 //      c_rarg0, c_rarg1, c_rarg2, c_rarg3, ... (param regs)
 //      rscratch1, rscratch2 (scratch regs)
 void InterpreterMacroAssembler::unlock_object(Register lock_reg)
diff --git a/src/cpu/aarch64/vm/interpreter_aarch64.hpp b/src/cpu/aarch64/vm/interpreter_aarch64.hpp
index b60841df9..bee0e5b1c 100644
--- a/src/cpu/aarch64/vm/interpreter_aarch64.hpp
+++ b/src/cpu/aarch64/vm/interpreter_aarch64.hpp
@@ -27,7 +27,7 @@
 
  public:
   static Address::ScaleFactor stackElementScale() {
-    return NOT_LP64(Address::times_4) LP64_ONLY(Address::times_8);
+    return Address::times_8;
   }
 
   // Offset from rsp (which points to the last stack element)
diff --git a/src/cpu/aarch64/vm/jni_aarch64.h b/src/cpu/aarch64/vm/jni_aarch64.h
index d724c8600..926863192 100644
--- a/src/cpu/aarch64/vm/jni_aarch64.h
+++ b/src/cpu/aarch64/vm/jni_aarch64.h
@@ -26,7 +26,7 @@
 #ifndef _JAVASOFT_JNI_MD_H_
 #define _JAVASOFT_JNI_MD_H_
 
-#if defined(SOLARIS) || defined(LINUX) || defined(_ALLBSD_SOURCE)
+#if defined(LINUX)
 
 #if defined(__GNUC__) && (__GNUC__ > 4) || (__GNUC__ == 4) && (__GNUC_MINOR__ > 2)
   #define JNIEXPORT     __attribute__((visibility("default")))
@@ -49,13 +49,6 @@
   typedef long long jlong;
 #endif
 
-#else
-  #define JNIEXPORT __declspec(dllexport)
-  #define JNIIMPORT __declspec(dllimport)
-  #define JNICALL __stdcall
-
-  typedef int jint;
-  typedef __int64 jlong;
 #endif
 
 typedef signed char jbyte;
diff --git a/src/cpu/aarch64/vm/methodHandles_aarch64.hpp b/src/cpu/aarch64/vm/methodHandles_aarch64.hpp
index 80c151c99..a0f98fc90 100644
--- a/src/cpu/aarch64/vm/methodHandles_aarch64.hpp
+++ b/src/cpu/aarch64/vm/methodHandles_aarch64.hpp
@@ -27,7 +27,7 @@
 
 // Adapters
 enum /* platform_dependent_constants */ {
-  adapter_code_size = NOT_LP64(16000 DEBUG_ONLY(+ 15000)) LP64_ONLY(32000 DEBUG_ONLY(+ 120000))
+  adapter_code_size = 32000 DEBUG_ONLY(+ 120000)
 };
 
 public:
diff --git a/src/cpu/aarch64/vm/register_definitions_aarch64.cpp b/src/cpu/aarch64/vm/register_definitions_aarch64.cpp
index 35deb6723..18b2d0e01 100644
--- a/src/cpu/aarch64/vm/register_definitions_aarch64.cpp
+++ b/src/cpu/aarch64/vm/register_definitions_aarch64.cpp
@@ -26,16 +26,7 @@
 #include "asm/assembler.hpp"
 #include "asm/register.hpp"
 #include "register_aarch64.hpp"
-#ifdef TARGET_ARCH_MODEL_x86_32
-# include "interp_masm_x86_32.hpp"
-#endif
-#ifdef TARGET_ARCH_MODEL_x86_64
-# include "interp_masm_x86_64.hpp"
-#endif
-
-#ifdef TARGET_ARCH_MODEL_aarch64
 # include "interp_masm_aarch64.hpp"
-#endif
 
 REGISTER_DEFINITION(Register, r0);
 REGISTER_DEFINITION(Register, r1);
diff --git a/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp b/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp
index 6b4ff0703..77424e181 100644
--- a/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp
+++ b/src/cpu/aarch64/vm/sharedRuntime_aarch64.cpp
@@ -63,6 +63,7 @@ class SimpleRuntimeFrame {
   };
 };
 
+// FIXME -- this is used by C1
 class RegisterSaver {
  public:
   static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
diff --git a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
index 5bb7a7b46..7ac713169 100644
--- a/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
+++ b/src/cpu/aarch64/vm/stubGenerator_aarch64.cpp
@@ -41,15 +41,6 @@
 #ifdef TARGET_OS_FAMILY_linux
 # include "thread_linux.inline.hpp"
 #endif
-#ifdef TARGET_OS_FAMILY_solaris
-# include "thread_solaris.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_windows
-# include "thread_windows.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_bsd
-# include "thread_bsd.inline.hpp"
-#endif
 #ifdef COMPILER2
 #include "opto/runtime.hpp"
 #endif
@@ -655,19 +646,6 @@ class StubGenerator: public StubCodeGenerator {
 
   address generate_get_previous_sp() { return 0; }
 
-  //----------------------------------------------------------------------------------------------------
-  // Support for void verify_mxcsr()
-  //
-  // This routine is used with -Xcheck:jni to verify that native
-  // JNI code does not return to Java code without restoring the
-  // MXCSR register to our expected state.
-
-  // NOTE: on x86 this is called from the cpp and template
-  // interpreters and internally from the call stub -- we can probbaly
-  // do without any equivalent for aarch64 for now at least
-
-  address generate_verify_mxcsr() { Unimplemented(); return 0; }
-
   // NOTE: these fixup routines appear only to be called from the
   // opto code (they are mentioned in x86_64.ad) so we can do
   // without them for now on aarch64
@@ -680,11 +658,6 @@ class StubGenerator: public StubCodeGenerator {
 
   address generate_d2l_fixup() { Unimplemented(); return 0; }
 
-  // NOTE: this appears only to be used internal to the x86 call stub
-  // to support the mxcsr code so we can do without it for now on aarch64
-
-  address generate_fp_mask(const char *stub_name, int64_t mask) { Unimplemented(); return 0; }
-
   // The following routine generates a subroutine to throw an
   // asynchronous UnknownError when an unsafe access gets a fault that
   // could not be reasonably prevented by the programmer.  (Example:
diff --git a/src/cpu/aarch64/vm/stubRoutines_aarch64.cpp b/src/cpu/aarch64/vm/stubRoutines_aarch64.cpp
index 782dc9063..ddbc523e4 100644
--- a/src/cpu/aarch64/vm/stubRoutines_aarch64.cpp
+++ b/src/cpu/aarch64/vm/stubRoutines_aarch64.cpp
@@ -29,15 +29,6 @@
 #ifdef TARGET_OS_FAMILY_linux
 # include "thread_linux.inline.hpp"
 #endif
-#ifdef TARGET_OS_FAMILY_solaris
-# include "thread_solaris.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_windows
-# include "thread_windows.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_bsd
-# include "thread_bsd.inline.hpp"
-#endif
 
 // Implementation of the platform-specific part of StubRoutines - for
 // a description of how to extend it, see the stubRoutines.hpp file.
@@ -45,8 +36,6 @@
 address StubRoutines::x86::_get_previous_fp_entry = NULL;
 address StubRoutines::x86::_get_previous_sp_entry = NULL;
 
-address StubRoutines::x86::_verify_mxcsr_entry = NULL;
-
 address StubRoutines::x86::_f2i_fixup = NULL;
 address StubRoutines::x86::_f2l_fixup = NULL;
 address StubRoutines::x86::_d2i_fixup = NULL;
@@ -55,4 +44,3 @@ address StubRoutines::x86::_float_sign_mask = NULL;
 address StubRoutines::x86::_float_sign_flip = NULL;
 address StubRoutines::x86::_double_sign_mask = NULL;
 address StubRoutines::x86::_double_sign_flip = NULL;
-address StubRoutines::x86::_mxcsr_std = NULL;
diff --git a/src/cpu/aarch64/vm/stubRoutines_aarch64.hpp b/src/cpu/aarch64/vm/stubRoutines_aarch64.hpp
index b3db0b2cf..dd18f9722 100644
--- a/src/cpu/aarch64/vm/stubRoutines_aarch64.hpp
+++ b/src/cpu/aarch64/vm/stubRoutines_aarch64.hpp
@@ -47,7 +47,6 @@ class x86 {
  private:
   static address _get_previous_fp_entry;
   static address _get_previous_sp_entry;
-  static address _verify_mxcsr_entry;
 
   static address _f2i_fixup;
   static address _f2l_fixup;
@@ -58,7 +57,6 @@ class x86 {
   static address _float_sign_flip;
   static address _double_sign_mask;
   static address _double_sign_flip;
-  static address _mxcsr_std;
 
  public:
 
@@ -72,11 +70,6 @@ class x86 {
     return _get_previous_sp_entry;
   }
 
-  static address verify_mxcsr_entry()
-  {
-    return _verify_mxcsr_entry;
-  }
-
   static address f2i_fixup()
   {
     return _f2i_fixup;
@@ -116,11 +109,6 @@ class x86 {
   {
     return _double_sign_flip;
   }
-
-  static address mxcsr_std()
-  {
-    return _mxcsr_std;
-  }
 };
 
 #endif // CPU_AARCH64_VM_STUBROUTINES_AARCH64_64_HPP
diff --git a/src/cpu/aarch64/vm/vm_version_aarch64.cpp b/src/cpu/aarch64/vm/vm_version_aarch64.cpp
index 48b4a1754..0817898d0 100644
--- a/src/cpu/aarch64/vm/vm_version_aarch64.cpp
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.cpp
@@ -31,15 +31,6 @@
 #ifdef TARGET_OS_FAMILY_linux
 # include "os_linux.inline.hpp"
 #endif
-#ifdef TARGET_OS_FAMILY_solaris
-# include "os_solaris.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_windows
-# include "os_windows.inline.hpp"
-#endif
-#ifdef TARGET_OS_FAMILY_bsd
-# include "os_bsd.inline.hpp"
-#endif
 
 #include "../../../../../simulator/simulator.hpp"
 
@@ -48,7 +39,6 @@ int VM_Version::_model;
 int VM_Version::_stepping;
 int VM_Version::_cpuFeatures;
 const char*           VM_Version::_features_str = "";
-VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
 
 static BufferBlob* stub_blob;
 static const int stub_size = 550;
diff --git a/src/cpu/aarch64/vm/vm_version_aarch64.hpp b/src/cpu/aarch64/vm/vm_version_aarch64.hpp
index 002aa3226..77811397d 100644
--- a/src/cpu/aarch64/vm/vm_version_aarch64.hpp
+++ b/src/cpu/aarch64/vm/vm_version_aarch64.hpp
@@ -30,192 +30,6 @@
 
 class VM_Version : public Abstract_VM_Version {
 public:
-  // cpuid result register layouts.  These are all unions of a uint32_t
-  // (in case anyone wants access to the register as a whole) and a bitfield.
-
-  union StdCpuid1Eax {
-    uint32_t value;
-    struct {
-      uint32_t stepping   : 4,
-               model      : 4,
-               family     : 4,
-               proc_type  : 2,
-                          : 2,
-               ext_model  : 4,
-               ext_family : 8,
-                          : 4;
-    } bits;
-  };
-
-  union StdCpuid1Ebx { // example, unused
-    uint32_t value;
-    struct {
-      uint32_t brand_id         : 8,
-               clflush_size     : 8,
-               threads_per_cpu  : 8,
-               apic_id          : 8;
-    } bits;
-  };
-
-  union StdCpuid1Ecx {
-    uint32_t value;
-    struct {
-      uint32_t sse3     : 1,
-                        : 2,
-               monitor  : 1,
-                        : 1,
-               vmx      : 1,
-                        : 1,
-               est      : 1,
-                        : 1,
-               ssse3    : 1,
-               cid      : 1,
-                        : 2,
-               cmpxchg16: 1,
-                        : 4,
-               dca      : 1,
-               sse4_1   : 1,
-               sse4_2   : 1,
-                        : 2,
-               popcnt   : 1,
-                        : 3,
-               osxsave  : 1,
-               avx      : 1,
-                        : 3;
-    } bits;
-  };
-
-  union StdCpuid1Edx {
-    uint32_t value;
-    struct {
-      uint32_t          : 4,
-               tsc      : 1,
-                        : 3,
-               cmpxchg8 : 1,
-                        : 6,
-               cmov     : 1,
-                        : 3,
-               clflush  : 1,
-                        : 3,
-               mmx      : 1,
-               fxsr     : 1,
-               sse      : 1,
-               sse2     : 1,
-                        : 1,
-               ht       : 1,
-                        : 3;
-    } bits;
-  };
-
-  union DcpCpuid4Eax {
-    uint32_t value;
-    struct {
-      uint32_t cache_type    : 5,
-                             : 21,
-               cores_per_cpu : 6;
-    } bits;
-  };
-
-  union DcpCpuid4Ebx {
-    uint32_t value;
-    struct {
-      uint32_t L1_line_size  : 12,
-               partitions    : 10,
-               associativity : 10;
-    } bits;
-  };
-
-  union TplCpuidBEbx {
-    uint32_t value;
-    struct {
-      uint32_t logical_cpus : 16,
-                            : 16;
-    } bits;
-  };
-
-  union ExtCpuid1Ecx {
-    uint32_t value;
-    struct {
-      uint32_t LahfSahf     : 1,
-               CmpLegacy    : 1,
-                            : 4,
-               lzcnt        : 1,
-               sse4a        : 1,
-               misalignsse  : 1,
-               prefetchw    : 1,
-                            : 22;
-    } bits;
-  };
-
-  union ExtCpuid1Edx {
-    uint32_t value;
-    struct {
-      uint32_t           : 22,
-               mmx_amd   : 1,
-               mmx       : 1,
-               fxsr      : 1,
-                         : 4,
-               long_mode : 1,
-               tdnow2    : 1,
-               tdnow     : 1;
-    } bits;
-  };
-
-  union ExtCpuid5Ex {
-    uint32_t value;
-    struct {
-      uint32_t L1_line_size : 8,
-               L1_tag_lines : 8,
-               L1_assoc     : 8,
-               L1_size      : 8;
-    } bits;
-  };
-
-  union ExtCpuid7Edx {
-    uint32_t value;
-    struct {
-      uint32_t               : 8,
-              tsc_invariance : 1,
-                             : 23;
-    } bits;
-  };
-
-  union ExtCpuid8Ecx {
-    uint32_t value;
-    struct {
-      uint32_t cores_per_cpu : 8,
-                             : 24;
-    } bits;
-  };
-
-  union SefCpuid7Eax {
-    uint32_t value;
-  };
-
-  union SefCpuid7Ebx {
-    uint32_t value;
-    struct {
-      uint32_t fsgsbase : 1,
-                        : 2,
-                   bmi1 : 1,
-                        : 1,
-                   avx2 : 1,
-                        : 2,
-                   bmi2 : 1,
-                        : 23;
-    } bits;
-  };
-
-  union XemXcr0Eax {
-    uint32_t value;
-    struct {
-      uint32_t x87 : 1,
-               sse : 1,
-               ymm : 1,
-                   : 29;
-    } bits;
-  };
-
 protected:
   static int _cpu;
   static int _model;
@@ -224,441 +38,18 @@ protected:
                                // 0 if this instruction is not available
   static const char* _features_str;
 
-  enum {
-    CPU_CX8    = (1 << 0), // next bits are from cpuid 1 (EDX)
-    CPU_CMOV   = (1 << 1),
-    CPU_FXSR   = (1 << 2),
-    CPU_HT     = (1 << 3),
-    CPU_MMX    = (1 << 4),
-    CPU_3DNOW_PREFETCH  = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
-                                    // may not necessarily support other 3dnow instructions
-    CPU_SSE    = (1 << 6),
-    CPU_SSE2   = (1 << 7),
-    CPU_SSE3   = (1 << 8), // SSE3 comes from cpuid 1 (ECX)
-    CPU_SSSE3  = (1 << 9),
-    CPU_SSE4A  = (1 << 10),
-    CPU_SSE4_1 = (1 << 11),
-    CPU_SSE4_2 = (1 << 12),
-    CPU_POPCNT = (1 << 13),
-    CPU_LZCNT  = (1 << 14),
-    CPU_TSC    = (1 << 15),
-    CPU_TSCINV = (1 << 16),
-    CPU_AVX    = (1 << 17),
-    CPU_AVX2   = (1 << 18)
-  } cpuFeatureFlags;
-
-  enum {
-    // AMD
-    CPU_FAMILY_AMD_11H       = 0x11,
-    // Intel
-    CPU_FAMILY_INTEL_CORE    = 6,
-    CPU_MODEL_NEHALEM        = 0x1e,
-    CPU_MODEL_NEHALEM_EP     = 0x1a,
-    CPU_MODEL_NEHALEM_EX     = 0x2e,
-    CPU_MODEL_WESTMERE       = 0x25,
-    CPU_MODEL_WESTMERE_EP    = 0x2c,
-    CPU_MODEL_WESTMERE_EX    = 0x2f,
-    CPU_MODEL_SANDYBRIDGE    = 0x2a,
-    CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
-    CPU_MODEL_IVYBRIDGE_EP   = 0x3a
-  } cpuExtendedFamily;
-
-  // cpuid information block.  All info derived from executing cpuid with
-  // various function numbers is stored here.  Intel and AMD info is
-  // merged in this block: accessor methods disentangle it.
-  //
-  // The info block is laid out in subblocks of 4 dwords corresponding to
-  // eax, ebx, ecx and edx, whether or not they contain anything useful.
-  struct CpuidInfo {
-    // cpuid function 0
-    uint32_t std_max_function;
-    uint32_t std_vendor_name_0;
-    uint32_t std_vendor_name_1;
-    uint32_t std_vendor_name_2;
-
-    // cpuid function 1
-    StdCpuid1Eax std_cpuid1_eax;
-    StdCpuid1Ebx std_cpuid1_ebx;
-    StdCpuid1Ecx std_cpuid1_ecx;
-    StdCpuid1Edx std_cpuid1_edx;
-
-    // cpuid function 4 (deterministic cache parameters)
-    DcpCpuid4Eax dcp_cpuid4_eax;
-    DcpCpuid4Ebx dcp_cpuid4_ebx;
-    uint32_t     dcp_cpuid4_ecx; // unused currently
-    uint32_t     dcp_cpuid4_edx; // unused currently
-
-    // cpuid function 7 (structured extended features)
-    SefCpuid7Eax sef_cpuid7_eax;
-    SefCpuid7Ebx sef_cpuid7_ebx;
-    uint32_t     sef_cpuid7_ecx; // unused currently
-    uint32_t     sef_cpuid7_edx; // unused currently
-
-    // cpuid function 0xB (processor topology)
-    // ecx = 0
-    uint32_t     tpl_cpuidB0_eax;
-    TplCpuidBEbx tpl_cpuidB0_ebx;
-    uint32_t     tpl_cpuidB0_ecx; // unused currently
-    uint32_t     tpl_cpuidB0_edx; // unused currently
-
-    // ecx = 1
-    uint32_t     tpl_cpuidB1_eax;
-    TplCpuidBEbx tpl_cpuidB1_ebx;
-    uint32_t     tpl_cpuidB1_ecx; // unused currently
-    uint32_t     tpl_cpuidB1_edx; // unused currently
-
-    // ecx = 2
-    uint32_t     tpl_cpuidB2_eax;
-    TplCpuidBEbx tpl_cpuidB2_ebx;
-    uint32_t     tpl_cpuidB2_ecx; // unused currently
-    uint32_t     tpl_cpuidB2_edx; // unused currently
-
-    // cpuid function 0x80000000 // example, unused
-    uint32_t ext_max_function;
-    uint32_t ext_vendor_name_0;
-    uint32_t ext_vendor_name_1;
-    uint32_t ext_vendor_name_2;
-
-    // cpuid function 0x80000001
-    uint32_t     ext_cpuid1_eax; // reserved
-    uint32_t     ext_cpuid1_ebx; // reserved
-    ExtCpuid1Ecx ext_cpuid1_ecx;
-    ExtCpuid1Edx ext_cpuid1_edx;
-
-    // cpuid functions 0x80000002 thru 0x80000004: example, unused
-    uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
-    uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
-    uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
-
-    // cpuid function 0x80000005 // AMD L1, Intel reserved
-    uint32_t     ext_cpuid5_eax; // unused currently
-    uint32_t     ext_cpuid5_ebx; // reserved
-    ExtCpuid5Ex  ext_cpuid5_ecx; // L1 data cache info (AMD)
-    ExtCpuid5Ex  ext_cpuid5_edx; // L1 instruction cache info (AMD)
-
-    // cpuid function 0x80000007
-    uint32_t     ext_cpuid7_eax; // reserved
-    uint32_t     ext_cpuid7_ebx; // reserved
-    uint32_t     ext_cpuid7_ecx; // reserved
-    ExtCpuid7Edx ext_cpuid7_edx; // tscinv
-
-    // cpuid function 0x80000008
-    uint32_t     ext_cpuid8_eax; // unused currently
-    uint32_t     ext_cpuid8_ebx; // reserved
-    ExtCpuid8Ecx ext_cpuid8_ecx;
-    uint32_t     ext_cpuid8_edx; // reserved
-
-    // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
-    XemXcr0Eax   xem_xcr0_eax;
-    uint32_t     xem_xcr0_edx; // reserved
-  };
-
-  // The actual cpuid info block
-  static CpuidInfo _cpuid_info;
-
-  // Extractors and predicates
-  static uint32_t extended_cpu_family() {
-    uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
-    result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
-    return result;
-  }
-
-  static uint32_t extended_cpu_model() {
-    uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
-    result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
-    return result;
-  }
-
-  static uint32_t cpu_stepping() {
-    uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
-    return result;
-  }
-
-  static uint logical_processor_count() {
-    uint result = threads_per_core();
-    return result;
-  }
-
-  static uint32_t feature_flags() {
-    uint32_t result = 0;
-    if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
-      result |= CPU_CX8;
-    if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
-      result |= CPU_CMOV;
-    if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
-        _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
-      result |= CPU_FXSR;
-    // HT flag is set for multi-core processors also.
-    if (threads_per_core() > 1)
-      result |= CPU_HT;
-    if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
-        _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
-      result |= CPU_MMX;
-    if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
-      result |= CPU_SSE;
-    if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
-      result |= CPU_SSE2;
-    if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
-      result |= CPU_SSE3;
-    if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
-      result |= CPU_SSSE3;
-    if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
-      result |= CPU_SSE4_1;
-    if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
-      result |= CPU_SSE4_2;
-    if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
-      result |= CPU_POPCNT;
-    if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
-        _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
-        _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
-        _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
-      result |= CPU_AVX;
-      if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
-        result |= CPU_AVX2;
-    }
-    if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
-      result |= CPU_TSC;
-    if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
-      result |= CPU_TSCINV;
-
-    // AMD features.
-    if (is_amd()) {
-      if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
-          (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
-        result |= CPU_3DNOW_PREFETCH;
-      if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
-        result |= CPU_LZCNT;
-      if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
-        result |= CPU_SSE4A;
-    }
-
-    return result;
-  }
-
   static void get_processor_features();
 
 public:
-  // Offsets for cpuid asm stub
-  static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
-  static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
-  static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
-  static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
-  static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
-  static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
-  static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
-  static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
-  static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
-  static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
-  static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
-  static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
-
   // Initialization
   static void initialize();
 
   // Asserts
   static void assert_is_initialized() {
-    assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
   }
 
-  //
-  // Processor family:
-  //       3   -  386
-  //       4   -  486
-  //       5   -  Pentium
-  //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
-  //              Pentium M, Core Solo, Core Duo, Core2 Duo
-  //    family 6 model:   9,        13,       14,        15
-  //    0x0f   -  Pentium 4, Opteron
-  //
-  // Note: The cpu family should be used to select between
-  //       instruction sequences which are valid on all Intel
-  //       processors.  Use the feature test functions below to
-  //       determine whether a particular instruction is supported.
-  //
-  static int  cpu_family()        { return _cpu;}
-  static bool is_P6()             { return cpu_family() >= 6; }
-  static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
-  static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
-
-  static bool supports_processor_topology() {
-    return (_cpuid_info.std_max_function >= 0xB) &&
-           // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
-           // Some cpus have max cpuid >= 0xB but do not support processor topology.
-           ((_cpuid_info.tpl_cpuidB0_eax & 0x1f | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
-  }
-
-  static uint cores_per_cpu()  {
-    uint result = 1;
-    if (is_intel()) {
-      if (supports_processor_topology()) {
-        result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
-                 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
-      } else {
-        result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
-      }
-    } else if (is_amd()) {
-      result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
-    }
-    return result;
-  }
-
-  static uint threads_per_core()  {
-    uint result = 1;
-    if (is_intel() && supports_processor_topology()) {
-      result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
-    } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
-      result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
-               cores_per_cpu();
-    }
-    return result;
-  }
-
-  static intx prefetch_data_size()  {
-    intx result = 0;
-    if (is_intel()) {
-      result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
-    } else if (is_amd()) {
-      result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
-    }
-    if (result < 32) // not defined ?
-      result = 32;   // 32 bytes by default on x86 and other x64
-    return result;
-  }
-
-  //
-  // Feature identification
-  //
-  static bool supports_cpuid()    { return _cpuFeatures  != 0; }
-  static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
-  static bool supports_cmov()     { return (_cpuFeatures & CPU_CMOV) != 0; }
-  static bool supports_fxsr()     { return (_cpuFeatures & CPU_FXSR) != 0; }
-  static bool supports_ht()       { return (_cpuFeatures & CPU_HT) != 0; }
-  static bool supports_mmx()      { return (_cpuFeatures & CPU_MMX) != 0; }
-  static bool supports_sse()      { return (_cpuFeatures & CPU_SSE) != 0; }
-  static bool supports_sse2()     { return (_cpuFeatures & CPU_SSE2) != 0; }
-  static bool supports_sse3()     { return (_cpuFeatures & CPU_SSE3) != 0; }
-  static bool supports_ssse3()    { return (_cpuFeatures & CPU_SSSE3)!= 0; }
-  static bool supports_sse4_1()   { return (_cpuFeatures & CPU_SSE4_1) != 0; }
-  static bool supports_sse4_2()   { return (_cpuFeatures & CPU_SSE4_2) != 0; }
-  static bool supports_popcnt()   { return (_cpuFeatures & CPU_POPCNT) != 0; }
-  static bool supports_avx()      { return (_cpuFeatures & CPU_AVX) != 0; }
-  static bool supports_avx2()     { return (_cpuFeatures & CPU_AVX2) != 0; }
-  static bool supports_tsc()      { return (_cpuFeatures & CPU_TSC)    != 0; }
-
-  // Intel features
-  static bool is_intel_family_core() { return is_intel() &&
-                                       extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
-
-  static bool is_intel_tsc_synched_at_init()  {
-    if (is_intel_family_core()) {
-      uint32_t ext_model = extended_cpu_model();
-      if (ext_model == CPU_MODEL_NEHALEM_EP     ||
-          ext_model == CPU_MODEL_WESTMERE_EP    ||
-          ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
-          ext_model == CPU_MODEL_IVYBRIDGE_EP) {
-        // <= 2-socket invariant tsc support. EX versions are usually used
-        // in > 2-socket systems and likely don't synchronize tscs at
-        // initialization.
-        // Code that uses tsc values must be prepared for them to arbitrarily
-        // jump forward or backward.
-        return true;
-      }
-    }
-    return false;
-  }
-
-  // AMD features
-  static bool supports_3dnow_prefetch()    { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
-  static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
-  static bool supports_lzcnt()    { return (_cpuFeatures & CPU_LZCNT) != 0; }
-  static bool supports_sse4a()    { return (_cpuFeatures & CPU_SSE4A) != 0; }
-
-  static bool is_amd_Barcelona()  { return is_amd() &&
-                                           extended_cpu_family() == CPU_FAMILY_AMD_11H; }
-
-  // Intel and AMD newer cores support fast timestamps well
-  static bool supports_tscinv_bit() {
-    return (_cpuFeatures & CPU_TSCINV) != 0;
-  }
-  static bool supports_tscinv() {
-    return supports_tscinv_bit() &&
-           ( (is_amd() && !is_amd_Barcelona()) ||
-             is_intel_tsc_synched_at_init() );
-  }
-
-  // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
-  static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
-                                           supports_sse3() && _model != 0x1C; }
-
-  static bool supports_compare_and_exchange() { return true; }
-
   static const char* cpu_features()           { return _features_str; }
 
-  static intx allocate_prefetch_distance() {
-    // This method should be called before allocate_prefetch_style().
-    //
-    // Hardware prefetching (distance/size in bytes):
-    // Pentium 3 -  64 /  32
-    // Pentium 4 - 256 / 128
-    // Athlon    -  64 /  32 ????
-    // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
-    // Core      - 128 /  64
-    //
-    // Software prefetching (distance in bytes / instruction with best score):
-    // Pentium 3 - 128 / prefetchnta
-    // Pentium 4 - 512 / prefetchnta
-    // Athlon    - 128 / prefetchnta
-    // Opteron   - 256 / prefetchnta
-    // Core      - 256 / prefetchnta
-    // It will be used only when AllocatePrefetchStyle > 0
-
-    intx count = AllocatePrefetchDistance;
-    if (count < 0) {   // default ?
-      if (is_amd()) {  // AMD
-        if (supports_sse2())
-          count = 256; // Opteron
-        else
-          count = 128; // Athlon
-      } else {         // Intel
-        if (supports_sse2())
-          if (cpu_family() == 6) {
-            count = 256; // Pentium M, Core, Core2
-          } else {
-            count = 512; // Pentium 4
-          }
-        else
-          count = 128; // Pentium 3 (and all other old CPUs)
-      }
-    }
-    return count;
-  }
-  static intx allocate_prefetch_style() {
-    assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
-    // Return 0 if AllocatePrefetchDistance was not defined.
-    return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
-  }
-
-  // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
-  // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
-  // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
-  // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
-
-  // gc copy/scan is disabled if prefetchw isn't supported, because
-  // Prefetch::write emits an inlined prefetchw on Linux.
-  // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
-  // The used prefetcht0 instruction works for both amd64 and em64t.
-  static intx prefetch_copy_interval_in_bytes() {
-    intx interval = PrefetchCopyIntervalInBytes;
-    return interval >= 0 ? interval : 576;
-  }
-  static intx prefetch_scan_interval_in_bytes() {
-    intx interval = PrefetchScanIntervalInBytes;
-    return interval >= 0 ? interval : 576;
-  }
-  static intx prefetch_fields_ahead() {
-    intx count = PrefetchFieldsAhead;
-    return count >= 0 ? count : 1;
-  }
 };
 
 #endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
diff --git a/src/cpu/aarch64/vm/vmreg_aarch64.cpp b/src/cpu/aarch64/vm/vmreg_aarch64.cpp
index 9d1611433..ec85a163e 100644
--- a/src/cpu/aarch64/vm/vmreg_aarch64.cpp
+++ b/src/cpu/aarch64/vm/vmreg_aarch64.cpp
@@ -45,6 +45,6 @@ void VMRegImpl::set_regName() {
   }
 
   for ( ; i < ConcreteRegisterImpl::number_of_registers ; i ++ ) {
-    regName[i] = "NON-GPR-FPR-XMM";
+    regName[i] = "NON-GPR-FPR";
   }
 }