Platform/DeveloperBox: make PCIe BME defer dip switch configurabledeveloper-box-from-hell

Tie DIP switch DSW3-5 to the dynamic PCD that defers enabling of the
PCIe Bus Master Enable bit to the first PciIo->Map() call made by the
driver. This helps identify drivers that don't bother to use Map/Unmap
at all, which is a violation of the UEFI spec.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

5 files changed, 16 insertions, 0 deletions

diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
index ef740882..c155b41f 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
@@ -152,6 +152,7 @@
 

   gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0x2E00FFC0

   gSynQuacerTokenSpaceGuid.PcdIgnoreFirstMemRegionGpioPin|3

+  gSynQuacerTokenSpaceGuid.PcdDeferBusMasterEnableGpioPin|4

 

   #

   # 96boards mezzanine support

diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc.inc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc.inc
index b85902a8..cd45143e 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc.inc
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc.inc
@@ -326,3 +326,5 @@
 [PcdsDynamicDefault]

   gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000

   gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF

+

+  gEfiMdeModulePkgTokenSpaceGuid.PcdDeferBusMasterEnableToPciIoMap|FALSE

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
index af8dfd12..3f6dbcec 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
@@ -164,6 +164,16 @@ PlatformPeim (
   }

 

   Value = 0;

+  Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdDeferBusMasterEnableGpioPin),

+             &Value);

+  if (!EFI_ERROR (Status) && Value != 0) {

+    DEBUG ((DEBUG_WARN, "%a: deferring PCI bus master enable to PciIo->Map() call\n",

+      __FUNCTION__));

+    Status = PcdSetBoolS (PcdDeferBusMasterEnableToPciIoMap, TRUE);

+    ASSERT_EFI_ERROR (Status);

+  }

+

+  Value = 0;

   Status = ReadGpioInput (Gpio, FixedPcdGet8 (PcdIgnoreFirstMemRegionGpioPin),

              &Value);

   if (!EFI_ERROR (Status) && Value != 0) {

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
index c4e53767..53124527 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
@@ -45,6 +45,7 @@
   gSynQuacerTokenSpaceGuid.PcdDramInfoBase

   gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin

   gSynQuacerTokenSpaceGuid.PcdIgnoreFirstMemRegionGpioPin

+  gSynQuacerTokenSpaceGuid.PcdDeferBusMasterEnableGpioPin

 

 [Ppis]

   gEdkiiEmbeddedGpioPpiGuid             ## CONSUMES

@@ -54,6 +55,7 @@
   gArmTokenSpaceGuid.PcdSystemMemoryBase

   gArmTokenSpaceGuid.PcdSystemMemorySize

   gSynQuacerTokenSpaceGuid.PcdPcieEnableMask

+  gEfiMdeModulePkgTokenSpaceGuid.PcdDeferBusMasterEnableToPciIoMap

 

 [Depex]

   gEdkiiEmbeddedGpioPpiGuid

diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec
index af22a383..2c83624d 100644
--- a/Silicon/Socionext/SynQuacer/SynQuacer.dec
+++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec
@@ -45,6 +45,7 @@
   gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin|0xFF|UINT8|0x00000006

 

   gSynQuacerTokenSpaceGuid.PcdIgnoreFirstMemRegionGpioPin|0xFF|UINT8|0x0000000A

+  gSynQuacerTokenSpaceGuid.PcdDeferBusMasterEnableGpioPin|0xFF|UINT8|0x0000000C

 

   gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005