diff options
Diffstat (limited to 'arch/arm64/include/asm')
| -rw-r--r-- | arch/arm64/include/asm/acpi.h | 139 | ||||
| -rw-r--r-- | arch/arm64/include/asm/cpu.h | 30 | ||||
| -rw-r--r-- | arch/arm64/include/asm/cputype.h | 11 | ||||
| -rw-r--r-- | arch/arm64/include/asm/io.h | 1 | ||||
| -rw-r--r-- | arch/arm64/include/asm/processor.h | 13 | ||||
| -rw-r--r-- | arch/arm64/include/asm/smp.h | 3 | ||||
| -rw-r--r-- | arch/arm64/include/asm/topology.h | 43 |
7 files changed, 240 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h new file mode 100644 index 000000000000..3d37c0ea02e7 --- /dev/null +++ b/arch/arm64/include/asm/acpi.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2013, Al Stone <al.stone@linaro.org> + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + */ + +#ifndef _ASM_ARM_ACPI_H +#define _ASM_ARM_ACPI_H + +#ifdef __KERNEL__ + +#include <acpi/pdc_arm64.h> + +#include <asm/cacheflush.h> + +#include <linux/init.h> + +#define COMPILER_DEPENDENT_INT64 long long +#define COMPILER_DEPENDENT_UINT64 unsigned long long + +#define MAX_LOCAL_APIC 256 +#define MAX_IO_APICS 64 + +/* + * Calling conventions: + * + * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads) + * ACPI_EXTERNAL_XFACE - External ACPI interfaces + * ACPI_INTERNAL_XFACE - Internal ACPI interfaces + * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces + */ +#define ACPI_SYSTEM_XFACE +#define ACPI_EXTERNAL_XFACE +#define ACPI_INTERNAL_XFACE +#define ACPI_INTERNAL_VAR_XFACE + +/* Asm macros */ +#define ACPI_ASM_MACROS +#define BREAKPOINT3 +#define ACPI_DISABLE_IRQS() local_irq_disable() +#define ACPI_ENABLE_IRQS() local_irq_enable() +#define ACPI_FLUSH_CPU_CACHE() flush_cache_all() + +/* Blob handling macros */ +#define ACPI_BLOB_HEADER_SIZE 8 + +int __acpi_acquire_global_lock(unsigned int *lock); +int __acpi_release_global_lock(unsigned int *lock); + +#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \ + ((Acq) = __acpi_acquire_global_lock(&facs->global_lock)) + +#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \ + ((Acq) = __acpi_release_global_lock(&facs->global_lock)) + +/* Basic configuration for ACPI */ +/* BOZO: hardware reduced acpi only? */ +#ifdef CONFIG_ACPI +extern int acpi_disabled; +extern int acpi_noirq; +extern int acpi_pci_disabled; +extern int acpi_strict; + +/* map logic cpu id to physical APIC id + * APIC = GIC cpu interface on ARM + */ +extern volatile int arm_cpu_to_apicid[NR_CPUS]; +extern int boot_cpu_apic_id; +#define cpu_physical_id(cpu) arm_cpu_to_apicid[cpu] + +struct acpi_arm_root { + phys_addr_t phys_address; + unsigned long size; +}; +extern struct acpi_arm_root acpi_arm_rsdp_info; + +/* Low-level suspend routine. */ +extern int acpi_suspend_lowlevel(void); + +extern void prefill_possible_map(void); + +/* Physical address to resume after wakeup */ +/* BOZO: was... +#define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start)) +*/ +#define acpi_wakeup_address (0) + + +static inline void disable_acpi(void) +{ + acpi_disabled = 1; + acpi_pci_disabled = 1; + acpi_noirq = 1; +} + +static inline bool arch_has_acpi_pdc(void) +{ + /* BOZO: replace x86 specific-ness here */ + return 0; /* always false for now */ +} + +static inline void arch_acpi_set_pdc_bits(u32 *buf) +{ + /* BOZO: replace x86 specific-ness here */ +} + +static inline void acpi_noirq_set(void) { acpi_noirq = 1; } +static inline void acpi_disable_pci(void) +{ + acpi_pci_disabled = 1; + acpi_noirq_set(); +} + +#else /* !CONFIG_ACPI */ +#define acpi_disabled 1 /* ACPI sometimes enabled on ARM */ +#define acpi_noirq 1 /* ACPI sometimes enabled on ARM */ +#define acpi_pci_disabled 1 /* ACPI PCI sometimes enabled on ARM */ +#define acpi_strict 1 /* no ACPI spec workarounds on ARM */ +#endif + +#endif /*__KERNEL__*/ + +#endif /*_ASM_ARM_ACPI_H*/ diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h new file mode 100644 index 000000000000..5613e097933a --- /dev/null +++ b/arch/arm64/include/asm/cpu.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2004-2005 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARM_CPU_H +#define __ASM_ARM_CPU_H + +#include <linux/percpu.h> +#include <linux/cpu.h> +#include <linux/topology.h> + +struct cpuinfo_arm { + struct cpu cpu; + u32 cpuid; +#ifdef CONFIG_SMP + unsigned int loops_per_jiffy; +#endif +}; + +#ifdef CONFIG_HOTPLUG_CPU +extern int arch_register_cpu(int cpu); +extern void arch_unregister_cpu(int cpu); +#endif + +DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data); + +#endif diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5fe138e0b828..58a595f8be4d 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -30,6 +30,17 @@ #define MPIDR_HWID_BITMASK 0xff00ffffff +#define MPIDR_SMP_BITMASK (0x1 << 30) +#define MPIDR_MT_BITMASK (0x1 << 24) + +#define MPIDR_LEVEL_BITS 8 +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_AFFINITY_LEVEL_0(mpidr) ((mpidr) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_1(mpidr) ((mpidr >> 8) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_2(mpidr) ((mpidr >> 16) & MPIDR_LEVEL_MASK) +#define MPIDR_AFFINITY_LEVEL_3(mpidr) ((mpidr >> 32) & MPIDR_LEVEL_MASK) + #define read_cpuid(reg) ({ \ u64 __val; \ asm("mrs %0, " reg : "=r" (__val)); \ diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 1d12f89140ba..30c4628f4254 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -234,6 +234,7 @@ extern void __iounmap(volatile void __iomem *addr); #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) #define ioremap_cached(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL)) +#define ioremap_cache(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL)) #define iounmap __iounmap #define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index ab239b2c456f..53326fd81897 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -155,6 +155,19 @@ static inline void spin_lock_prefetch(const void *x) prefetchw(x); } +/* + * Not all ARM devices have ACPI, but some do + * BOZO: is this correct? + */ +#ifdef CONFIG_ACPI +enum idle_boot_override { IDLE_NO_OVERRIDE = 0, IDLE_HALT, IDLE_NOMWAIT, + IDLE_POLL, IDLE_FORCE_MWAIT }; + +extern unsigned long boot_option_idle_override; +#endif + +/* end BOZO */ + #define HAVE_ARCH_PICK_MMAP_LAYOUT #endif diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 4b8023c5d146..95c9f5865000 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -63,6 +63,9 @@ extern struct secondary_data secondary_data; extern void secondary_holding_pen(void); extern volatile unsigned long secondary_holding_pen_release; +extern int __cpu_disable(void); +extern void __cpu_die(unsigned int cpu); + extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h new file mode 100644 index 000000000000..06440d4c54c1 --- /dev/null +++ b/arch/arm64/include/asm/topology.h @@ -0,0 +1,43 @@ +#ifndef _ASM_ARM64_TOPOLOGY_H +#define _ASM_ARM64_TOPOLOGY_H + +#ifdef CONFIG_ARM64_CPU_TOPOLOGY + +#include <linux/cpumask.h> + +struct cputopo_arm64 { + int thread_id; + int core_id; + int socket_id; + cpumask_t thread_sibling; + cpumask_t core_sibling; +}; + +DECLARE_PER_CPU(struct cputopo_arm64, cpu_topology); + +#define cpu_topo(cpu) per_cpu(cpu_topology, cpu) + +#define topology_physical_package_id(cpu) (cpu_topo(cpu).socket_id) +#define topology_core_id(cpu) (cpu_topo(cpu).core_id) +#define topology_core_cpumask(cpu) (&cpu_topo(cpu).core_sibling) +#define topology_thread_cpumask(cpu) (&cpu_topo(cpu).thread_sibling) + +#define mc_capable() (cpu_topo(0).socket_id != -1) +#define smt_capable() (cpu_topo(0).thread_id != -1) + +void init_cpu_topology(void); +void store_cpu_topology(unsigned int cpuid); +const struct cpumask *cpu_coregroup_mask(int cpu); +void arch_fix_phys_package_id(int num, u32 slot); + +#else + +static inline void arch_fix_phys_package_id(int num, u32 slot) {} +static inline void init_cpu_topology(void) { } +static inline void store_cpu_topology(unsigned int cpuid) { } + +#endif + +#include <asm-generic/topology.h> + +#endif /* _ASM_ARM64_TOPOLOGY_H */ |