diff options
author | Zeng Tao <prime.zeng@hisilicon.com> | 2019-01-31 00:22:23 +0800 |
---|---|---|
committer | Jérôme Forissier <jerome.forissier@linaro.org> | 2019-02-22 09:26:59 +0100 |
commit | b7667020c9146b9dc760174406a42ab62b167f6b (patch) | |
tree | 65239c0036e5553515b3d9f4306b2d2ececd2ac7 /core/arch/arm/plat-hisilicon/psci.c | |
parent | 7bd5ce8f03604e864613aaa73b721fcb30fbf10e (diff) |
Add support for Hisilicon Hi3519AV100 DEMO board
Hi3519AV100 is a high-performance and low-power 4K
Smart IP Camera SoC designed for IP cameras, action cameras,
panoramic cameras, rear view mirrors, and UAVs. Hi3519A
V100 introduces H.265/H.264 encoding and decoding, with
performance up to 4K x 2K@60 fps and 1080p@240 fps.
For more information:
http://www.hisilicon.com/en/Products/ProductList/Surveillance
This patch has been tested using the following step,
1. Patch the uboot and Linux kernel with OP-TEE support if required
2. build step:
(1) make CROSS_COMPILE=arm-himix200-linux- PLATFORM=hisilicon
PLATFORM_FLAVOR=hi3519av100_demo (OPTEE-OS build)
(2) make CROSS_COMPILE_HOST=arm-himix200-linux- (OPTEE_CLIENT build)
(3) cross_compile openssl and replace optee_test/host/libopenssl
(4) make CROSS_COMPILE_HOST=arm-himix200-linux-
CROSS_COMPILE_TA=arm-himix200-linux-
TA_DEV_KIT_DIR=../optee_os/out/arm-plat-hisilicon/export-ta_arm32
COMPILE_NS_USER=32 (OPTEE_TEST build)
3. mkimage -A arm -T kernel -O tee -C none -d tee.bin uTee.optee
4. Boot setting in uboot:
nand read 0x22007fc0 0x100000 0x400000; /* load kernel */
tftp 0x30000000 uTee.optee;bootm 0x30000000;
5. after Linux startup, run daemon tee-supplicant
6. run xtest
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
Diffstat (limited to 'core/arch/arm/plat-hisilicon/psci.c')
-rw-r--r-- | core/arch/arm/plat-hisilicon/psci.c | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/core/arch/arm/plat-hisilicon/psci.c b/core/arch/arm/plat-hisilicon/psci.c new file mode 100644 index 00000000..dad87030 --- /dev/null +++ b/core/arch/arm/plat-hisilicon/psci.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (c) 2019, HiSilicon Technologies Co., Ltd. + */ + +#include <console.h> +#include <io.h> +#include <kernel/generic_boot.h> +#include <kernel/misc.h> +#include <kernel/panic.h> +#include <kernel/pm_stubs.h> +#include <mm/core_mmu.h> +#include <mm/core_memprot.h> +#include <platform_config.h> +#include <stdint.h> +#include <sm/optee_smc.h> +#include <sm/psci.h> +#include <tee/entry_std.h> +#include <tee/entry_fast.h> + +#define REG_CPU_SUSSYS_RESET 0xcc +#define REG_CPU_START_COMMAND 0x0 +#define REG_CPU_START_ADDR 0x4 +#define REG_SYSCTRL_RESET 0x4 +#define RELEASE_CORE_MASK (BIT32(25) | BIT32(1)) + +int psci_features(uint32_t psci_fid) +{ + switch (psci_fid) { + case PSCI_PSCI_FEATURES: + case PSCI_VERSION: + case PSCI_SYSTEM_RESET: +#ifdef CFG_BOOT_SECONDARY_REQUEST + case PSCI_CPU_ON: +#endif + return PSCI_RET_SUCCESS; + default: + return PSCI_RET_NOT_SUPPORTED; + } +} + +uint32_t psci_version(void) +{ + return PSCI_VERSION_1_0; +} + +void psci_system_reset(void) +{ + vaddr_t sysctrl = core_mmu_get_va(SYS_CTRL_BASE, MEM_AREA_IO_SEC); + + if (!sysctrl) { + EMSG("no sysctrl mapping, hang here"); + panic(); + } + + io_write32(sysctrl + REG_SYSCTRL_RESET, 0xdeadbeef); +} + +#ifdef CFG_BOOT_SECONDARY_REQUEST +int psci_cpu_on(uint32_t core_idx, uint32_t entry, + uint32_t context_id) +{ + uint32_t val = 0; + size_t pos = get_core_pos_mpidr(core_idx); + vaddr_t bootsram = core_mmu_get_va(BOOTSRAM_BASE, MEM_AREA_IO_SEC); + vaddr_t crg = core_mmu_get_va(CPU_CRG_BASE, MEM_AREA_IO_SEC); + + if (!bootsram || !crg) { + EMSG("No bootsram or crg mapping"); + return PSCI_RET_INVALID_PARAMETERS; + } + + if ((pos == 0) || (pos >= CFG_TEE_CORE_NB_CORE)) + return PSCI_RET_INVALID_PARAMETERS; + + /* set secondary core's NS entry addresses */ + generic_boot_set_core_ns_entry(pos, entry, context_id); + + val = virt_to_phys((void *)TEE_TEXT_VA_START); + io_write32(bootsram + REG_CPU_START_ADDR, val); + io_write32(bootsram + REG_CPU_START_COMMAND, 0xe51ff004); + + /* release secondary core */ + io_clrbits32(crg + REG_CPU_SUSSYS_RESET, RELEASE_CORE_MASK); + + return PSCI_RET_SUCCESS; +} +#endif |