diff options
| author | Fangsuo Wu <fangsuowu@asrmicro.com> | 2019-07-10 15:15:32 +0800 |
|---|---|---|
| committer | Jérôme Forissier <jerome.forissier@linaro.org> | 2019-07-30 13:42:36 +0200 |
| commit | d0d82b526534f8680ca0d3a3ac5014bfa39e35ac (patch) | |
| tree | b65a46db9c28a85f8b680600a7f221367bdc384a | |
| parent | 667b10f6f1b668c624a8d6f82cee63e27ec50803 (diff) | |
core: mmu: Update TCR_EL1 register when new physical address added
Suppose in init stage all physical memory registered is in 0-4G,
the IPS bits (bit34-32) is set 0. Later a physical address 0x100000000
is dynamically mapping with core_mmu_add_mapping, since 0x100000000
is higher than 4G, the IPS bits of TCR_EL1 register should be updated
to 0x1. Otherwise the below panic occurs:
E/TC:00 check_pa_matches_va:1805 va 0x82a00000 maps 0x100000000, expect 0x0
As currently TCR_EL1 register is only set in init stage, this patch
also updates the register in core_mmu_add_mapping.
Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
| -rw-r--r-- | core/arch/arm/mm/core_mmu.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/core/arch/arm/mm/core_mmu.c b/core/arch/arm/mm/core_mmu.c index 80452277..2de1fe21 100644 --- a/core/arch/arm/mm/core_mmu.c +++ b/core/arch/arm/mm/core_mmu.c @@ -1699,6 +1699,9 @@ bool core_mmu_add_mapping(enum teecore_memtypes type, paddr_t addr, size_t len) map->attr = core_mmu_type_to_attr(type); map->pa = p; + /* Update TCR_EL1 with possiable maximum physical address change */ + core_mmu_set_max_pa(map->pa + map->size); + set_region(&tbl_info, map); /* Make sure the new entry is visible before continuing. */ |