diff options
| author | Mourad Goumrhar <Mourad.Goumrhar@se.com> | 2019-06-14 10:50:45 +0100 |
|---|---|---|
| committer | Ryan Harkin <ryan.harkin@linaro.org> | 2020-07-24 18:02:33 +0100 |
| commit | 7b6bffc8d38fa3b6903eceb5a448a2da2b4666df (patch) | |
| tree | 9362b85851428fcf608655d3728009056d98313c | |
| parent | c633822d804b1f6f2c329bd8b5638d5063de65ea (diff) | |
Update DDR mapping to fit in first 128MB of DDR
Update optee after DDR memory layout changes
88000000 - Unallocated
87C00000 - TEE/TA RAM 4M
87A00000 - TEE NS Shmem 2M
87800000 - U-Boot 2M
87700000 - DTB
85000000 - Tmp FIT verification 39M
80008000 - Kernel + InitRAMfs ~80M
OP-TEE is moved to the end of the first 128MB bank on DDR.
Signed-off-by: Mourad Goumrhar <Mourad.Goumrhar@se.com>
| -rw-r--r-- | core/arch/arm/plat-rzn1/platform_config.h | 23 |
1 files changed, 9 insertions, 14 deletions
diff --git a/core/arch/arm/plat-rzn1/platform_config.h b/core/arch/arm/plat-rzn1/platform_config.h index 762c3887..79d6a91d 100644 --- a/core/arch/arm/plat-rzn1/platform_config.h +++ b/core/arch/arm/plat-rzn1/platform_config.h @@ -43,17 +43,15 @@ // The LCES memory map is designed as if there are two DRAM banks -// DRAM0 is always 64 MB, Trusted area are located at the end +// DRAM0 is always 128 MB, Trusted area is located at the end // DRAM1 stand for the remaining DRAM up to the maximum -// The following configuration fits for a total DRAM size of 128 MB - -// 0x8800_0000 (DRAM1_END)-------------------+ -// | U-Boot/Linux NON-SECURE 64 MB | DRAM1_SIZE -// 0x8400_0000 (DRAM1_BASE)------------------+ +// 0x9000_0000 (DRAM1_END)-------------------+ +// | U-Boot/Linux NON-SECURE 128 MB | DRAM1_SIZE +// 0x8800_0000 (DRAM1_BASE)------------------+ // | Trusted RAM (TA/TEE) SECURE 4 MB | TZDRAM_SIZE // | Shared memory NON-SECURE 2 MB | TEE_SHMEM_SIZE -// | U-Boot/Linux NON-SECURE 58 MB | DRAM0_SIZE_NSEC +// | U-Boot/Linux NON-SECURE 122 MB | // 0x8000_0000 (DRAM0_BASE)------------------+ // 0x2010_0000 ------------------------------+ @@ -62,19 +60,16 @@ // | TEE RAM: SECURE 624 KB | TZSRAM_SIZE // 0x2000_0000 (TZRAM)-----------------------+ -#define DRAMx_TOTAL_SIZE 0x08000000 // 128 MB - -// Only care about first 64MB of DRAM, aka. DRAM0 - #define DRAM0_BASE 0x80000000 -#define DRAM0_SIZE 0x04000000 -#define DRAM0_END (DRAM0_BASE + DRAM0_SIZE) +#define DRAM0_SIZE 0x08000000 // 128MB // Available memories +#define TZDRAM_SIZE 0x00400000 // 4MB +#define TEE_SHMEM_SIZE 0x00200000 // 2MB +#define TZDRAM_BASE (DRAM0_BASE + DRAM0_SIZE - TZDRAM_SIZE) #define TZSRAM_BASE 0x20000000 #define TZSRAM_SIZE 0x0009C000 // 624KB -#define TZDRAM_BASE (DRAM0_END - TZDRAM_SIZE) #define TZDRAM_SIZE 0x00400000 // 4MB // Choose location of TEE code |