diff options
| author | Etienne Carriere <etienne.carriere@linaro.org> | 2020-02-14 17:16:52 +0100 |
|---|---|---|
| committer | Jérôme Forissier <jerome@forissier.org> | 2020-02-17 09:18:37 +0100 |
| commit | 52ae776eaddaedde1dfede231cf02cae32aa0f42 (patch) | |
| tree | 6236c3a8ee298ea4297ff9f26232bd4a292c6b9e | |
| parent | 7c1d10cede85fa325eeb345e429dfa26b4e8a3c5 (diff) | |
core: aslr: fix cached_mem_end update
Fix update of cache_mem_end that corrupts CPU register R4 used to
store a boot argument in Aarch32.
Fixes: 487fd6828322 ("core: aslr: apply load offset to cached_mem_end")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
| -rw-r--r-- | core/arch/arm/kernel/generic_entry_a32.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/core/arch/arm/kernel/generic_entry_a32.S b/core/arch/arm/kernel/generic_entry_a32.S index c4fa7652..008bfb2e 100644 --- a/core/arch/arm/kernel/generic_entry_a32.S +++ b/core/arch/arm/kernel/generic_entry_a32.S @@ -505,9 +505,10 @@ shadow_stack_access_ok: * Update cached_mem_end address with load offset since it was * calculated before relocation. */ - ldr r4, cached_mem_end - add r4, r4, r0 - str r4, cached_mem_end + ldr r2, cached_mem_end + add r2, r2, r0 + str r2, cached_mem_end + bl relocate #endif |