core: read thread_vector_table from assembly

Reads and returns thread_vector_table directly from assembly instead of
saving the return value from generic_boot_init_primary(). With this
generic_boot_init_primary() is declared in the same way when configured
with or without TF-A.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

4 files changed, 17 insertions, 21 deletions

diff --git a/core/arch/arm/include/kernel/generic_boot.h b/core/arch/arm/include/kernel/generic_boot.h
index 24e22e47..bdc6c23a 100644
--- a/core/arch/arm/include/kernel/generic_boot.h
+++ b/core/arch/arm/include/kernel/generic_boot.h
@@ -42,15 +42,13 @@ struct boot_embdata {
 extern uint8_t embedded_secure_dtb[];
 extern const struct core_mmu_config boot_mmu_config;
 
+/* @nsec_entry is unused if using CFG_WITH_ARM_TRUSTED_FW */
+void generic_boot_init_primary(unsigned long pageable_part,
+			       unsigned long nsec_entry, unsigned long fdt);
 #if defined(CFG_WITH_ARM_TRUSTED_FW)
 unsigned long cpu_on_handler(unsigned long a0, unsigned long a1);
-struct thread_vector_table *
-generic_boot_init_primary(unsigned long pageable_part, unsigned long unused,
-			  unsigned long fdt);
 unsigned long generic_boot_cpu_on_handler(unsigned long a0, unsigned long a1);
 #else
-void generic_boot_init_primary(unsigned long pageable_part,
-			       unsigned long nsec_entry, unsigned long fdt);
 void generic_boot_init_secondary(unsigned long nsec_entry);
 #endif
 
diff --git a/core/arch/arm/kernel/generic_boot.c b/core/arch/arm/kernel/generic_boot.c
index 9162d2b0..97991045 100644
--- a/core/arch/arm/kernel/generic_boot.c
+++ b/core/arch/arm/kernel/generic_boot.c
@@ -1206,15 +1206,19 @@ static void init_secondary_helper(unsigned long nsec_entry)
 	DMSG("Secondary CPU Switching to normal world boot");
 }
 
-#if defined(CFG_WITH_ARM_TRUSTED_FW)
-struct thread_vector_table *
-generic_boot_init_primary(unsigned long pageable_part, unsigned long u __unused,
-			  unsigned long fdt)
+void generic_boot_init_primary(unsigned long pageable_part,
+			       unsigned long nsec_entry __maybe_unused,
+			       unsigned long fdt)
 {
-	init_primary_helper(pageable_part, PADDR_INVALID, fdt);
-	return &thread_vector_table;
+	unsigned long e = PADDR_INVALID;
+
+#if !defined(CFG_WITH_ARM_TRUSTED_FW)
+	e = nsec_entry;
+#endif
+	init_primary_helper(pageable_part, e, fdt);
 }
 
+#if defined(CFG_WITH_ARM_TRUSTED_FW)
 unsigned long generic_boot_cpu_on_handler(unsigned long a0 __maybe_unused,
 				     unsigned long a1 __unused)
 {
@@ -1223,12 +1227,6 @@ unsigned long generic_boot_cpu_on_handler(unsigned long a0 __maybe_unused,
 	return 0;
 }
 #else
-void generic_boot_init_primary(unsigned long pageable_part,
-			       unsigned long nsec_entry, unsigned long fdt)
-{
-	init_primary_helper(pageable_part, nsec_entry, fdt);
-}
-
 void generic_boot_init_secondary(unsigned long nsec_entry)
 {
 	init_secondary_helper(nsec_entry);
diff --git a/core/arch/arm/kernel/generic_entry_a32.S b/core/arch/arm/kernel/generic_entry_a32.S
index d2e9ff00..67a7133a 100644
--- a/core/arch/arm/kernel/generic_entry_a32.S
+++ b/core/arch/arm/kernel/generic_entry_a32.S
@@ -518,7 +518,6 @@ shadow_stack_access_ok:
 	mov	r1, r5		/* ns-entry address */
 	mov	r2, r6		/* DT address */
 	bl	generic_boot_init_primary
-	mov	r4, r0		/* save entry test vector */
 
 	/*
 	 * In case we've touched memory that secondary CPUs will use before
@@ -553,8 +552,9 @@ shadow_stack_access_ok:
 #if defined(CFG_WITH_ARM_TRUSTED_FW)
 	ldr	r0, =boot_mmu_config
 	ldr	r0, [r0, #CORE_MMU_CONFIG_LOAD_OFFSET]
+	ldr	r1, =thread_vector_table
 	/* Pass the vector address returned from main_init */
-	sub	r1, r4, r0
+	sub	r1, r1, r0
 #else
 	/* realy standard bootarg #1 and #2 to non secure entry */
 	mov	r4, #0
diff --git a/core/arch/arm/kernel/generic_entry_a64.S b/core/arch/arm/kernel/generic_entry_a64.S
index bfb97a5c..17f80cb4 100644
--- a/core/arch/arm/kernel/generic_entry_a64.S
+++ b/core/arch/arm/kernel/generic_entry_a64.S
@@ -206,7 +206,6 @@ clear_nex_bss:
 	 * they have turned on their D-cache, clean and invalidate the
 	 * D-cache before exiting to normal world.
 	 */
-	mov	x19, x0
 	adr_l	x0, __text_start
 	ldr	x1, cached_mem_end
 	sub	x1, x1, x0
@@ -228,7 +227,8 @@ clear_nex_bss:
 	 * called with MMU off.
 	 */
 	ldr	x0, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET
-	sub	x1, x19, x0
+	adr	x1, thread_vector_table
+	sub	x1, x1, x0
 	mov	x0, #TEESMC_OPTEED_RETURN_ENTRY_DONE
 	smc	#0
 	b	.	/* SMC should not return */