diff options
| author | Mourad Goumrhar <Mourad.Goumrhar@se.com> | 2019-08-26 09:23:51 +0200 |
|---|---|---|
| committer | Mourad Goumrhar <Mourad.Goumrhar@se.com> | 2019-08-30 12:55:24 +0200 |
| commit | c7233274cca3996e42fdd587aa93abbc23381b45 (patch) | |
| tree | f8c2c78a59a09f17ee0bafddb2616806d77c7436 | |
| parent | f3138ce25f8a3e37ad24180bf3b5a54e232e8dcf (diff) | |
RZN1: increase and move TEE/TA RAM and SHMEMlinaro-rel-2019.09-warriorlinaro-20190902-001rmh-optee-3.3
This patch comfortably increases the TEE and TA RAM sizes as well as
SHMEM to make sure all xtest regression tests pass.
The location of the secure TEE and TA areas are moved across the
128M boundary.
Signed-off-by: Mourad Goumrhar <Mourad.Goumrhar@se.com>
| -rw-r--r-- | core/arch/arm/plat-rzn1/platform_config.h | 48 |
1 files changed, 15 insertions, 33 deletions
diff --git a/core/arch/arm/plat-rzn1/platform_config.h b/core/arch/arm/plat-rzn1/platform_config.h index 79d6a91d..9bbbbe9e 100644 --- a/core/arch/arm/plat-rzn1/platform_config.h +++ b/core/arch/arm/plat-rzn1/platform_config.h @@ -43,66 +43,48 @@ // The LCES memory map is designed as if there are two DRAM banks -// DRAM0 is always 128 MB, Trusted area is located at the end +// DRAM0 is always 128 MB // DRAM1 stand for the remaining DRAM up to the maximum +// Trusted area is located at its start // 0x9000_0000 (DRAM1_END)-------------------+ -// | U-Boot/Linux NON-SECURE 128 MB | DRAM1_SIZE +// | U-Boot/Linux NON-SECURE 118 MB | DRAM1_SIZE +// | TA RAM SECURE 8 MB | | +// | TEE RAM SECURE 2 MB | | TZDRAM // 0x8800_0000 (DRAM1_BASE)------------------+ -// | Trusted RAM (TA/TEE) SECURE 4 MB | TZDRAM_SIZE -// | Shared memory NON-SECURE 2 MB | TEE_SHMEM_SIZE -// | U-Boot/Linux NON-SECURE 122 MB | +// | Shared memory NON-SECURE 4 MB | TEE_SHMEM_SIZE +// | U-Boot/Linux NON-SECURE 124 MB | // 0x8000_0000 (DRAM0_BASE)------------------+ -// 0x2010_0000 ------------------------------+ -// | Cortex-M3 NON-SECURE 400 KB | -// 0x2009_C000 ------------------------------+ -// | TEE RAM: SECURE 624 KB | TZSRAM_SIZE -// 0x2000_0000 (TZRAM)-----------------------+ - #define DRAM0_BASE 0x80000000 #define DRAM0_SIZE 0x08000000 // 128MB +#define DRAM1_BASE (DRAM0_BASE + DRAM0_SIZE) // Available memories -#define TZDRAM_SIZE 0x00400000 // 4MB -#define TEE_SHMEM_SIZE 0x00200000 // 2MB -#define TZDRAM_BASE (DRAM0_BASE + DRAM0_SIZE - TZDRAM_SIZE) - -#define TZSRAM_BASE 0x20000000 -#define TZSRAM_SIZE 0x0009C000 // 624KB -#define TZDRAM_SIZE 0x00400000 // 4MB +#define TZDRAM_SIZE 0x00A00000 // 10MB +#define TEE_SHMEM_SIZE 0x00400000 // 4MB +#define TZDRAM_BASE DRAM1_BASE // Choose location of TEE code //#define TEE_RAM_START TZSRAM_BASE #define TEE_RAM_START TZDRAM_BASE -// Configuration when TEE resides in SRAM -#if (TEE_RAM_START == TZSRAM_BASE) -#define TEE_RAM_PH_SIZE TZSRAM_SIZE -#define TEE_LOAD_ADDR (TZSRAM_BASE+0x20000) // 128KB offset -#define TA_RAM_OFFSET 0 -#endif - // Configuration when TEE resides in DDR #if (TEE_RAM_START == TZDRAM_BASE) -#define TEE_RAM_PH_SIZE 0x00100000 // 1MB +#define TEE_RAM_PH_SIZE 0x00200000 // 2MB #define TEE_LOAD_ADDR TZDRAM_BASE #define TA_RAM_OFFSET TEE_RAM_PH_SIZE #endif // Other TEE configuration - #define CFG_TEE_CORE_NB_CORE 2 #define TEE_RAM_VA_SIZE TEE_RAM_PH_SIZE -// TA are located in secured part (end) of DRAM0 - +// TA are located in secured part (start) of DRAM1 #define TA_RAM_START (TZDRAM_BASE+TA_RAM_OFFSET) #define TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE-TA_RAM_OFFSET, CORE_MMU_DEVICE_SIZE) -// SHM is above TA in non-secure DRAM, rigth under secure DRAM - -#define TEE_SHMEM_START (TZDRAM_BASE - TEE_SHMEM_SIZE) -#define TEE_SHMEM_SIZE 0x00200000 // 2MB +// SHM is below TZDRAM in non-secure DRAM0 +#define TEE_SHMEM_START (DRAM1_BASE - TEE_SHMEM_SIZE) #endif /* PLATFORM_CONFIG_H */ |