diff options
author | Tushar Behera <tushar.behera@linaro.org> | 2014-02-10 10:07:39 +0530 |
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committer | Tushar Behera <tushar.behera@linaro.org> | 2014-02-10 10:07:42 +0530 |
commit | 8283acc0bf7db35fc23524ab8826ac0669aa1e9f (patch) | |
tree | cd5bebda3348d6c463bcaf12eebeaf1abc6ae7b2 | |
parent | 6415bf60c44b2f726d066d627e34c9ac7290d46f (diff) |
arndale_octa: Set EPLL as parent of AUDSS clockssamsung-lt-arndale_octa-2014.02
AUDSS clocks can have two parents, 24MHz crystal or the EPLL. By default
the crystal is set as the parent, but the rate is not sufficient for higher
frequency audio playback. Setting EPLL as the parent is required for
better audio playback.
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
-rw-r--r-- | arch/arm/include/asm/arch-exynos/cpu.h | 1 | ||||
-rw-r--r-- | board/samsung/smdk5420/smdk5420.c | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 180b89483..f3aeda2c9 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -57,6 +57,7 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5 */ +#define EXYNOS5_AUDSS_BASE 0x03810000 #if defined(CONFIG_CPU_EXYNOS5420) #define EXYNOS5_GPIO_PART4_BASE 0x14010000 #else diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index da1719bf5..f2a64e7ce 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -50,6 +50,15 @@ DECLARE_GLOBAL_DATA_PTR; unsigned int pmic; unsigned int nr_dram_banks = 0; +static void clk_audss_init(void) +{ + unsigned int val = readl(EXYNOS5_AUDSS_BASE); + + val |= 0x1; + + writel(val, EXYNOS5_AUDSS_BASE); +} + static int init_nr_dram_banks(void) { int evt_num = (GetEvtNum()<<12)|(GetEvtSubNum()<<8)|(GetPopOption()<<4)|(GetDdrType()); @@ -139,6 +148,8 @@ int board_init(void) display_boot_device_info(); + clk_audss_init(); + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; |