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Diffstat (limited to 'drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h')
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h115
1 files changed, 97 insertions, 18 deletions
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index 7aecf920f9b9..8a4a2d161a29 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
-- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
-- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
-
-Copyright (C) 2013-2022 by the following authors:
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
+- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
+
+Copyright (C) 2013-2023 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -76,6 +76,10 @@ enum vgt_event_type {
VS_FETCH_DONE = 27,
FACENESS_FLUSH = 28,
WT_DONE_TS = 8,
+ START_FRAGMENT_CTRS = 13,
+ STOP_FRAGMENT_CTRS = 14,
+ START_COMPUTE_CTRS = 15,
+ STOP_COMPUTE_CTRS = 16,
FLUSH_SO_0 = 17,
FLUSH_SO_1 = 18,
FLUSH_SO_2 = 19,
@@ -86,7 +90,7 @@ enum vgt_event_type {
PC_CCU_FLUSH_DEPTH_TS = 28,
PC_CCU_FLUSH_COLOR_TS = 29,
BLIT = 30,
- UNK_25 = 37,
+ LRZ_CLEAR = 37,
LRZ_FLUSH = 38,
BLIT_OP_FILL_2D = 39,
BLIT_OP_COPY_2D = 40,
@@ -95,6 +99,20 @@ enum vgt_event_type {
UNK_2C = 44,
UNK_2D = 45,
CACHE_INVALIDATE = 49,
+ LABEL = 63,
+ CCU_INVALIDATE_DEPTH = 24,
+ CCU_INVALIDATE_COLOR = 25,
+ CCU_RESOLVE_CLEAN = 26,
+ CCU_FLUSH_DEPTH = 28,
+ CCU_FLUSH_COLOR = 29,
+ CCU_RESOLVE = 30,
+ CCU_END_RESOLVE_GROUP = 31,
+ CCU_CLEAN_DEPTH = 32,
+ CCU_CLEAN_COLOR = 33,
+ CACHE_RESET = 48,
+ CACHE_CLEAN = 49,
+ CACHE_FLUSH7 = 50,
+ CACHE_INVALIDATE7 = 51,
};
enum pc_di_primtype {
@@ -290,6 +308,9 @@ enum adreno_pm4_type3_packets {
IN_INCR_UPDT_CONST = 86,
IN_INCR_UPDT_INSTR = 87,
PKT4 = 4,
+ IN_IB_END = 10,
+ IN_GMU_INTERRUPT = 11,
+ IN_PREEMPT = 15,
CP_SCRATCH_WRITE = 76,
CP_REG_TO_MEM_OFFSET_MEM = 116,
CP_REG_TO_MEM_OFFSET_REG = 114,
@@ -297,10 +318,20 @@ enum adreno_pm4_type3_packets {
CP_WAIT_TWO_REGS = 112,
CP_MEMCPY = 117,
CP_SET_BIN_DATA5_OFFSET = 46,
+ CP_CONTEXT_SWITCH = 84,
CP_SET_CTXSWITCH_IB = 85,
CP_REG_WRITE = 109,
CP_START_BIN = 80,
CP_END_BIN = 81,
+ CP_PREEMPT_DISABLE = 108,
+ CP_WAIT_TIMESTAMP = 20,
+ CP_THREAD_CONTROL = 23,
+ CP_CONTEXT_REG_BUNCH2 = 93,
+ CP_UNK15 = 21,
+ CP_UNK16 = 22,
+ CP_UNK18 = 24,
+ CP_UNK1B = 27,
+ CP_UNK49 = 73,
};
enum adreno_state_block {
@@ -480,6 +511,13 @@ enum reg_tracker {
TRACK_CNTL_REG = 1,
TRACK_RENDER_CNTL = 2,
UNK_EVENT_WRITE = 4,
+ TRACK_LRZ = 8,
+};
+
+enum cp_thread {
+ CP_SET_THREAD_BR = 1,
+ CP_SET_THREAD_BV = 2,
+ CP_SET_THREAD_BOTH = 3,
};
#define REG_CP_LOAD_STATE_0 0x00000000
@@ -1256,6 +1294,10 @@ static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
}
+#define REG_CP_SET_BIN_DATA5_7 0x00000007
+
+#define REG_CP_SET_BIN_DATA5_9 0x00000009
+
#define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000
#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000
#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16
@@ -2202,7 +2244,18 @@ static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
{
return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
}
-#define A6XX_CP_REG_TEST_0_WAIT_FOR_ME 0x02000000
+#define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME 0x02000000
+#define A6XX_CP_REG_TEST_0_PRED_BIT__MASK 0x7c000000
+#define A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT 26
+static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val)
+{
+ return ((val) << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK;
+}
+#define A6XX_CP_REG_TEST_0_PRED_UPDATE 0x80000000
+
+#define REG_A6XX_CP_REG_TEST_PRED_MASK 0x00000001
+
+#define REG_A6XX_CP_REG_TEST_PRED_VAL 0x00000002
#define REG_CP_COND_REG_EXEC_0 0x00000000
#define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff
@@ -2211,6 +2264,12 @@ static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
{
return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
}
+#define CP_COND_REG_EXEC_0_PRED_BIT__MASK 0x007c0000
+#define CP_COND_REG_EXEC_0_PRED_BIT__SHIFT 18
+static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val)
+{
+ return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK;
+}
#define CP_COND_REG_EXEC_0_BINNING 0x02000000
#define CP_COND_REG_EXEC_0_GMEM 0x04000000
#define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
@@ -2308,13 +2367,17 @@ static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
}
#define REG_CP_REG_WRITE_0 0x00000000
-#define CP_REG_WRITE_0_TRACKER__MASK 0x00000007
+#define CP_REG_WRITE_0_TRACKER__MASK 0x0000000f
#define CP_REG_WRITE_0_TRACKER__SHIFT 0
static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
{
return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
}
+#define REG_CP_REG_WRITE_1 0x00000001
+
+#define REG_CP_REG_WRITE_2 0x00000002
+
#define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000
#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff
#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0
@@ -2361,5 +2424,21 @@ static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
#define REG_CP_START_BIN_BODY_DWORDS 0x00000004
+#define REG_CP_WAIT_TIMESTAMP_0 0x00000000
+
+#define REG_CP_WAIT_TIMESTAMP_ADDR 0x00000001
+
+#define REG_CP_WAIT_TIMESTAMP_TIMESTAMP 0x00000003
+
+#define REG_CP_THREAD_CONTROL_0 0x00000000
+#define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003
+#define CP_THREAD_CONTROL_0_THREAD__SHIFT 0
+static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val)
+{
+ return ((val) << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK;
+}
+#define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000
+#define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000
+
#endif /* ADRENO_PM4_XML */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 06:46:37 +0000