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author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-03-06 20:02:00 +0300 |
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committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-03-06 20:02:00 +0300 |
commit | 71f66a632705bbc18c2c239a2453048e71f6ac0e (patch) | |
tree | 0da5d6fd1c8eb3982f6ce123157276bc3214f047 /rr-cache/ff1da602272756b8afa3ab68f352105db6606030 | |
parent | 3f9ace97a31de049706d6858ff367f7849bb127d (diff) |
New rr-cache entries from ci-merge
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'rr-cache/ff1da602272756b8afa3ab68f352105db6606030')
-rw-r--r-- | rr-cache/ff1da602272756b8afa3ab68f352105db6606030/preimage | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/rr-cache/ff1da602272756b8afa3ab68f352105db6606030/preimage b/rr-cache/ff1da602272756b8afa3ab68f352105db6606030/preimage new file mode 100644 index 0000000..a1d1220 --- /dev/null +++ b/rr-cache/ff1da602272756b8afa3ab68f352105db6606030/preimage @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +<<<<<<< + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" +======= +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +>>>>>>> + +title: Qualcomm SNPS eUSB2 phy controller + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + +description: + eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + +properties: + compatible: + const: qcom,sm8550-snps-eusb2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: ref + + clock-names: + items: + - const: ref + +<<<<<<< + resets: + maxItems: 1 + + phys: + maxItems: 1 +======= + usb-repeater: +>>>>>>> + description: + Phandle to eUSB2 to USB 2.0 repeater + + vdd-supply: + description: + Phandle to 0.88V regulator supply to PHY digital circuit. + + vdda12-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + +<<<<<<< +======= + resets: + maxItems: 1 + description: + Phandle to reset to phy block. + +>>>>>>> +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - vdd-supply + - vdda12-supply + - resets + +additionalProperties: false + +examples: + - | +<<<<<<< + #include <dt-bindings/clock/qcom,gcc-sm8550.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,tcsrcc-sm8550.h> +======= + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,sm8550-tcsr.h> +>>>>>>> + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x88e3000 0x154>; + #phy-cells = <0>; + +<<<<<<< + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_src", "ref"; +======= + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; +>>>>>>> + + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; |