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authorBhupesh Sharma <bhupesh.sharma@linaro.org>2022-01-28 19:48:14 +0530
committerBhupesh Sharma <bhupesh.sharma@linaro.org>2022-01-28 19:48:14 +0530
commit1a3eaee2d36f0fac8f0dc01e25bf7745eedee807 (patch)
treed24a8a696be03d5be386be8554b765c8cee96ffc
parenta98bbc34054f08a26c488ec5b3eab9766911981f (diff)
New rr-cache entries from ci-merge
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
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+ Qualcomm SPMI PMICs multi-function device bindings
+
+The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
+PMICs. These PMICs use a QPNP scheme through SPMI interface.
+QPNP is effectively a partitioning scheme for dividing the SPMI extended
+register space up into logical pieces, and set of fixed register
+locations/definitions within these regions, with some of these regions
+specifically used for interrupt handling.
+
+The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
+interfaced to the chip via the SPMI (System Power Management Interface) bus.
+Support for multiple independent functions are implemented by splitting the
+16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
+each. A function can consume one or more of these fixed-size register regions.
+
+Required properties:
+- compatible: Should contain one of:
+<<<<<<<
+ "qcom,pm660",
+ "qcom,pm660l",
+=======
+ "qcom,pm8941",
+ "qcom,pm8841",
+ "qcom,pma8084",
+ "qcom,pm8019",
+ "qcom,pm8226",
+ "qcom,pm8110",
+ "qcom,pma8084",
+ "qcom,pmi8962",
+ "qcom,pmd9635",
+ "qcom,pm8994",
+ "qcom,pmi8994",
+ "qcom,pm8916",
+ "qcom,pm8004",
+ "qcom,pm8909",
+ "qcom,pm8950",
+ "qcom,pmi8950",
+ "qcom,pm8998",
+ "qcom,pmi8998",
+ "qcom,pm8005",
+ "qcom,pm8350",
+ "qcom,pm8350b",
+ "qcom,pm8350c",
+ "qcom,pmk8350",
+>>>>>>>
+ "qcom,pm7325",
+ "qcom,pm8004",
+ "qcom,pm8005",
+ "qcom,pm8019",
+ "qcom,pm8028",
+ "qcom,pm8110",
+ "qcom,pm8150",
+ "qcom,pm8150b",
+ "qcom,pm8150c",
+ "qcom,pm8150l",
+ "qcom,pm8226",
+ "qcom,pm8350c",
+ "qcom,pm8841",
+ "qcom,pm8901",
+ "qcom,pm8909",
+ "qcom,pm8916",
+ "qcom,pm8941",
+ "qcom,pm8950",
+ "qcom,pm8994",
+ "qcom,pm8998",
+ "qcom,pma8084",
+ "qcom,pmd9635",
+ "qcom,pmi8950",
+ "qcom,pmi8962",
+ "qcom,pmi8994",
+ "qcom,pmi8998",
+ "qcom,pmk8002",
+ "qcom,pmk8350",
+ "qcom,pmr735a",
+<<<<<<<
+ "qcom,pmr735b",
+
+=======
+ "qcom,smb2351",
+>>>>>>>
+ or generalized "qcom,spmi-pmic".
+- reg: Specifies the SPMI USID slave address for this device.
+ For more information see:
+ Documentation/devicetree/bindings/spmi/spmi.yaml
+
+Required properties for peripheral child nodes:
+- compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
+
+Optional properties for peripheral child nodes:
+- interrupts: Interrupts are specified as a 4-tuple. For more information
+ see:
+ Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
+- interrupt-names: Corresponding interrupt name to the interrupts property
+
+Each child node of SPMI slave id represents a function of the PMIC. In the
+example below the rtc device node represents a peripheral of pm8941
+SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
+
+Example:
+
+ spmi {
+ compatible = "qcom,spmi-pmic-arb";
+
+ pm8941@0 {
+ compatible = "qcom,pm8941", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+
+ rtc {
+ compatible = "qcom,rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "alarm";
+ };
+ };
+
+ pm8941@1 {
+ compatible = "qcom,pm8941", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+
+ regulator {
+ compatible = "qcom,regulator";
+ regulator-name = "8941_boost";
+ };
+ };
+ };