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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright 2017-2018 NXP
*/
#ifndef __IMX7_GPC_REGS_H__
#define __IMX7_GPC_REGS_H__
#define GPC_CPU_PGC_SW_PUP_REQ 0x0F0
#define GPC_CPU_PGC_SW_PDN_REQ 0x0FC
#define GPC_CPU_PGC_SW_PUP_STATUS 0x130
#define BP_GPC_CPU_PGC_SW_PUP_REQ_CORE1_A7_SW_PUP_REQ 1
#define BM_GPC_CPU_PGC_SW_PUP_REQ_CORE1_A7_SW_PUP_REQ \
BIT32(BP_GPC_CPU_PGC_SW_PUP_REQ_CORE1_A7_SW_PUP_REQ)
#define BP_GPC_CPU_PGC_SW_PUP_STATUS_CORE1_A7_SW_PUP_STATUS 1
#define BM_GPC_CPU_PGC_SW_PUP_STATUS_CORE1_A7_SW_PUP_STATUS \
BIT32(BP_GPC_CPU_PGC_SW_PUP_STATUS_CORE1_A7_SW_PUP_STATUS)
/*
* GPC Registers - PGC
*/
#define GPC_PGC_A7CORE1_CTRL 0x840
#define BP_GPC_PGC_nCTRL_PCR 0
#define BM_GPC_PGC_nCTRL_PCR BIT32(BP_GPC_PGC_nCTRL_PCR)
#endif /* __IMX7_GPC_REGS_H__ */
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