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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright 2017-2018 NXP
*/
#ifndef __IMX6_SRC_REGS_H__
#define __IMX6_SRC_REGS_H__
#define SRC_SCR 0x0000
#define SRC_GPR1 0x0020
#define BP_SRC_SCR_CORE1_RST 14
#define BM_SRC_SCR_CORE1_RST BIT32(BP_SRC_SCR_CORE1_RST)
#define BP_SRC_SCR_CORE1_ENABLE 22
#define BM_SRC_SCR_CORE1_ENABLE BIT32(BP_SRC_SCR_CORE1_ENABLE)
#define BP_SRC_SCR_CORE2_ENABLE 23
#define BM_SRC_SCR_CORE2_ENABLE BIT32(BP_SRC_SCR_CORE2_ENABLE)
#define BP_SRC_SCR_CORE3_ENABLE 24
#define BM_SRC_SCR_CORE3_ENABLE BIT32(BP_SRC_SCR_CORE3_ENABLE)
#define BM_SRC_SCR_CPU_ENABLE_ALL (BM_SRC_SCR_CORE1_ENABLE | \
BM_SRC_SCR_CORE2_ENABLE | \
BM_SRC_SCR_CORE3_ENABLE)
#endif /* __IMX6_SRC_REGS_H__ */
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