porting guide: update mandated platform settings

Generic code expects platform sets TZDRAM_BASE, TZDRAM_SIZE,
TEE_RAM_START, TEE_RAM_VA_SIZE, TA_RAM_START, TA_RAM_SIZE,
TEE_SHMEM_START, TEE_SHMEM_SIZE and TEE_LOAD_ADDR.

Generic code with pager enable expects also TZSRAM_BASE, TZSRAM_SIZE
and TEE_RAM_PH_SIZE.

DRAM0_BASE/SIZE is not required by the generic code.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

1 files changed, 42 insertions, 19 deletions

diff --git a/documentation/porting_guidelines.md b/documentation/porting_guidelines.md
index c8e1d210..eecdd91b 100644
--- a/documentation/porting_guidelines.md
+++ b/documentation/porting_guidelines.md
@@ -66,6 +66,35 @@ Applications, which may be added to macros used by the build system. Please see
 It is recommended to use a existing platform configuration file as a starting
 point. For instance, [core/arch/arm/plat-hikey/conf.mk].
 
+The platform `conf.mk` file should at least define the default platform flavor
+for the platform, the core configurations (architecture and number of cores),
+the main configuration directives (generic boot, arm trusted firmware support,
+generic time source, console driver, etc...) and some platform default
+configuration settings.
+
+```makefile
+PLATFORM_FLAVOR ?= hikey
+
+include core/arch/arm/cpu/cortex-armv8-0.mk
+
+$(call force,CFG_TEE_CORE_NB_CORE,8)
+$(call force,CFG_GENERIC_BOOT,y)
+$(call force,CFG_PL011,y)
+$(call force,CFG_PM_STUBS,y)
+$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
+$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
+$(call force,CFG_WITH_LPAE,y)
+
+ta-targets = ta_arm32
+ta-targets += ta_arm64
+
+CFG_NUM_THREADS ?= 8
+CFG_CRYPTO_WITH_CE ?= y
+CFG_WITH_STACK_CANARIES ?= y
+CFG_CONSOLE_UART ?= 3
+CFG_DRAM_SIZE_GB ?= 2
+```
+
 ##### main.c
 This platform specific file will contain power management handlers and code
 related to the UART. We will talk more about the information related to the
@@ -143,33 +172,27 @@ could look like this:
 #define CONSOLE_BAUDRATE	115200
 #define CONSOLE_UART_CLK_IN_HZ	19200000
 
-#define DRAM0_BASE		0x00000000
-#define DRAM0_SIZE		0x40000000
-
-/* Below ARM-TF */
-#define TEE_SHMEM_START		0x08000000
-#define TEE_SHMEM_SIZE		(4 * 1024 * 1024)
-
-/* If your device has SRAM */
+/* Optional: when used with CFG_WITH_PAGER, defines the device SRAM */
 #define TZSRAM_BASE		0x3F000000
 #define TZSRAM_SIZE		(200 * 1024)
 
-/* Otherwise or in addition, use DDR */
+/* Mandatory main secure RAM usually DDR */
 #define TZDRAM_BASE		0x60000000
 #define TZDRAM_SIZE		(32 * 1024 * 1024)
 
-#define CFG_TEE_CORE_NB_CORE	4
-
-#define TEE_RAM_VA_SIZE	(4 * 1024 * 1024)
-
-#define CFG_TEE_LOAD_ADDR	(TZDRAM_BASE + 0x20000)
-
-#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+/* Mandatory TEE RAM location and core load address */
 #define TEE_RAM_START		TZDRAM_BASE
+#define TEE_RAM_PH_SIZE		TEE_RAM_VA_SIZE
+#define TEE_RAM_VA_SIZE		(4 * 1024 * 1024)
+#define TEE_LOAD_ADDR		(TZDRAM_BASE + 0x20000)
 
-#define TA_RAM_START		ROUNDUP((TZDRAM_BASE + TEE_RAM_VA_SIZE), \
-					CORE_MMU_DEVICE_SIZE)
-#define TA_RAM_SIZE		(16 * 1024 * 1024)
+/* Mandatory TA RAM (external less secure RAM) */
+#define TA_RAM_START		(TZDRAM_BASE + TEE_RAM_VA_SIZE)
+#define TA_RAM_SIZE		(TZDRAM_SIZE - TEE_RAM_VA_SIZE)
+
+/* Mandatory: for static SHM, need a hardcoded physical address */
+#define TEE_SHMEM_START		0x08000000
+#define TEE_SHMEM_SIZE		(4 * 1024 * 1024)
 
 #endif /* PLATFORM_CONFIG_H */
 ```