diff options
author | Bai Ping <ping.bai@nxp.com> | 2017-12-05 09:48:36 +0800 |
---|---|---|
committer | Silvano di Ninno <silvano.dininno@nxp.com> | 2018-08-02 15:37:22 +0200 |
commit | 5a8d1e1e17e6c5bc04856e8656d396780c937908 (patch) | |
tree | 0cf104b8439e74459779b1f81b2c57d269bb7175 | |
parent | 7f12720655ce54c40ad38a58a45de7fea36bcd33 (diff) |
MLK-17082-01 core: arm: imx: Add imx6sl evk board support
Add i.MX6SL EVK board support.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
-rw-r--r-- | core/arch/arm/plat-imx/conf.mk | 21 | ||||
-rw-r--r-- | core/arch/arm/plat-imx/config/imx6sl.h | 104 | ||||
-rw-r--r-- | core/arch/arm/plat-imx/imx-common.c | 4 | ||||
-rw-r--r-- | core/arch/arm/plat-imx/imx_csu.c | 10 | ||||
-rw-r--r-- | core/arch/arm/plat-imx/platform_config.h | 3 | ||||
-rw-r--r-- | core/arch/arm/plat-imx/sub.mk | 2 | ||||
-rw-r--r-- | core/arch/arm/plat-imx/tzasc.c | 22 |
7 files changed, 161 insertions, 5 deletions
diff --git a/core/arch/arm/plat-imx/conf.mk b/core/arch/arm/plat-imx/conf.mk index 78a4962a..11b8a424 100644 --- a/core/arch/arm/plat-imx/conf.mk +++ b/core/arch/arm/plat-imx/conf.mk @@ -6,7 +6,7 @@ mx6dl-flavorlist = mx6dlsabresd mx6dlsabreauto mx6q-flavorlist = mx6qsabrelite mx6qsabresd mx6qsabreauto mx6qp-flavorlist = mx6qpsabresd mx6qpsabreauto mx6s-flavorlist = -mx6sl-flavorlist = +mx6sl-flavorlist = mx6slevk mx6sll-flavorlist = mx6sx-flavorlist = mx6sxsabresd mx6sxsabreauto mx6ul-flavorlist = mx6ulevk mx6ul9x9evk @@ -46,6 +46,10 @@ else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist))) $(call force,CFG_MX6,y) $(call force,CFG_MX6SX,y) $(call force,CFG_TEE_CORE_NB_CORE,1) +else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist))) +$(call force,CFG_MX6,y) +$(call force,CFG_MX6SL,y) +$(call force,CFG_TEE_CORE_NB_CORE,1) else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist))) $(call force,CFG_MX7,y) $(call force,CFG_TEE_CORE_NB_CORE,2) @@ -78,9 +82,9 @@ $(call force,CFG_BOOT_SYNC_CPU,n) $(call force,CFG_BOOT_SECONDARY_REQUEST,n) endif -# i.MX6 Solo/SoloX/DualLite/Dual/Quad specific config +# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) \ - $(CFG_MX6S) $(CFG_MX6SX)), y) + $(CFG_MX6S) $(CFG_MX6SX) $(CFG_MX6SL)), y) include core/arch/arm/cpu/cortex-a9.mk $(call force,CFG_MX6,y) $(call force,CFG_PL310,y) @@ -241,6 +245,17 @@ CFG_BOOT_SYNC_CPU = n CFG_BOOT_SECONDARY_REQUEST = y endif +ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk)) +CFG_DT ?= y +CFG_NS_ENTRY_ADDR ?= 0x80800000 +CFG_DT_ADDR ?= 0x83000000 +CFG_DDR_SIZE ?= 0x20000000 +CFG_SHMEM_SIZE ?= 0x00200000 +CFG_PSCI_ARM32 ?= y +CFG_BOOT_SYNC_CPU = n +CFG_BOOT_SECONDARY_REQUEST = n +endif + ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd)) CFG_DT ?= y CFG_NS_ENTRY_ADDR ?= 0x80800000 diff --git a/core/arch/arm/plat-imx/config/imx6sl.h b/core/arch/arm/plat-imx/config/imx6sl.h new file mode 100644 index 00000000..6b7090bc --- /dev/null +++ b/core/arch/arm/plat-imx/config/imx6sl.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright 2017-2018 NXP + * + */ + +#ifndef _CONFIG_IMX6SL_H +#define _CONFIG_IMX6SL_H + +#ifndef CFG_UART_BASE +#define CFG_UART_BASE (UART1_BASE) +#endif + +#define DRAM0_BASE 0x80000000 +#define DRAM0_SIZE CFG_DDR_SIZE + +#define CONSOLE_UART_BASE (CFG_UART_BASE) + +/* + * PL310 TAG RAM Control Register + * + * bit[10:8]:1 - 2 cycle of write accesses latency + * bit[6:4]:1 - 2 cycle of read accesses latency + * bit[2:0]:1 - 2 cycle of setup latency + */ +#ifndef PL310_TAG_RAM_CTRL_INIT +#define PL310_TAG_RAM_CTRL_INIT 0x00000111 +#endif + +/* + * PL310 DATA RAM Control Register + * + * bit[10:8]:2 - 3 cycle of write accesses latency + * bit[6:4]:2 - 3 cycle of read accesses latency + * bit[2:0]:2 - 3 cycle of setup latency + */ +#ifndef PL310_DATA_RAM_CTRL_INIT +#define PL310_DATA_RAM_CTRL_INIT 0x00000222 +#endif + +/* + * PL310 Auxiliary Control Register + * + * I/Dcache prefetch enabled (bit29:28=2b11) + * NS can access interrupts (bit27=1) + * NS can lockown cache lines (bit26=1) + * Pseudo-random replacement policy (bit25=0) + * Force write allocated (default) + * Shared attribute internally ignored (bit22=1, bit13=0) + * Parity disabled (bit21=0) + * Event monitor disabled (bit20=0) + * Platform fmavor specific way config (dual / quad): + * - 64kb way size (bit19:17=3b011) + * - 16-way associciativity (bit16=1) + * Platform fmavor specific way config (dual lite / solo): + * - 32kb way size (bit19:17=3b010) + * - no 16-way associciativity (bit16=0) + * Store buffer device limitation enabled (bit11=1) + * Cacheable accesses have high prio (bit10=0) + * Full Line Zero (FLZ) disabled (bit0=0) + */ +#ifndef PL310_AUX_CTRL_INIT +#define PL310_AUX_CTRL_INIT 0x3C430800 +#endif + +/* + * PL310 Prefetch Control Register + * + * Double linefill disabled (bit30=0) + * I/D prefetch enabled (bit29:28=2b11) + * Prefetch drop enabled (bit24=1) + * Incr double linefill disable (bit23=0) + * Prefetch offset = 7 (bit4:0) + */ +#define PL310_PREFETCH_CTRL_INIT 0x31000007 + +/* + * PL310 Power Register + * + * Dynamic clock gating enabled + * Standby mode enabled + */ +#define PL310_POWER_CTRL_INIT 0x00000003 + +/* + * SCU Invalidate Register + * + * Invalidate all registers + */ +#define SCU_INV_CTRL_INIT 0xFFFFFFFF + +/* + * SCU Access Register + * - both secure CPU access SCU + */ +#define SCU_SAC_CTRL_INIT 0x0000000F + +/* + * SCU NonSecure Access Register + * - both nonsec cpu access SCU, private and global timer + */ +#define SCU_NSAC_CTRL_INIT 0x00000FFF + +#endif diff --git a/core/arch/arm/plat-imx/imx-common.c b/core/arch/arm/plat-imx/imx-common.c index 05d6bd21..2f67247a 100644 --- a/core/arch/arm/plat-imx/imx-common.c +++ b/core/arch/arm/plat-imx/imx-common.c @@ -22,8 +22,10 @@ static uint32_t imx_digproc(void) anatop_addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC); /* TODO: Handle SL here */ -#ifdef CFG_MX7 +#if defined CFG_MX7 reg = read32(anatop_addr + HW_ANADIG_DIGPROG_IMX7D); +#elif defined CFG_MX6SL + reg = read32(anatop_addr + HW_ANADIG_DIGPROG_IMX6SL); #else reg = read32(anatop_addr + HW_ANADIG_DIGPROG); #endif diff --git a/core/arch/arm/plat-imx/imx_csu.c b/core/arch/arm/plat-imx/imx_csu.c index 963183e8..5f8205c6 100644 --- a/core/arch/arm/plat-imx/imx_csu.c +++ b/core/arch/arm/plat-imx/imx_csu.c @@ -29,6 +29,14 @@ const struct csu_setting csu_setting_imx6ul[] = { {(-1), 0}, }; +const struct csu_setting csu_setting_imx6sl[] = { + {13, 0xFF0033}, /* Protect ROMCP */ + {14, 0x3F00FF}, /* Protect OCOTP */ + {16, 0xFF0033}, /* Protect TZASC */ + {26, 0xFF0033}, /* Protect OCRAM */ + {(-1), 0}, +}; + const struct csu_setting csu_setting_imx6sx[] = { {13, 0xFF0033}, /* Protect ROMCP */ {14, 0x3F00FF}, /* Protect OCOTP */ @@ -55,6 +63,8 @@ TEE_Result csu_init(void) csu_setting = csu_setting_imx6sx; } else if (soc_is_imx6ul() || soc_is_imx6ull()) { csu_setting = csu_setting_imx6ul; + } else if (soc_is_imx6sl()) { + csu_setting = csu_setting_imx6sl; } else if (soc_is_imx6()) { csu_setting = csu_setting_imx6; } else if (soc_is_imx7ds()) { diff --git a/core/arch/arm/plat-imx/platform_config.h b/core/arch/arm/plat-imx/platform_config.h index bcb7445b..0f1c3cdf 100644 --- a/core/arch/arm/plat-imx/platform_config.h +++ b/core/arch/arm/plat-imx/platform_config.h @@ -51,6 +51,9 @@ defined(CFG_MX6DL) || defined(CFG_MX6S) /* For i.MX6 Quad SABRE Lite and Smart Device board */ #include <config/imx6qdlsolo.h> +/* For i.MX 6SL */ +#elif defined(CFG_MX6SL) +#include <config/imx6sl.h> #else #error "Unknown platform flavor" #endif diff --git a/core/arch/arm/plat-imx/sub.mk b/core/arch/arm/plat-imx/sub.mk index b07a24da..cff570cb 100644 --- a/core/arch/arm/plat-imx/sub.mk +++ b/core/arch/arm/plat-imx/sub.mk @@ -12,7 +12,7 @@ asm-defines-y += imx_pm_asm_defines.c endif ifneq (,$(filter y, $(CFG_MX6Q) $(CFG_MX6QP) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \ - $(CFG_MX6SX))) + $(CFG_MX6SL) $(CFG_MX6SX))) srcs-y += a9_plat_init.S srcs-$(CFG_SM_PLATFORM_HANDLER) += sm_platform_handler.c endif diff --git a/core/arch/arm/plat-imx/tzasc.c b/core/arch/arm/plat-imx/tzasc.c index 862dcb11..bb199495 100644 --- a/core/arch/arm/plat-imx/tzasc.c +++ b/core/arch/arm/plat-imx/tzasc.c @@ -204,6 +204,28 @@ static int board_imx_tzasc_configure(vaddr_t addr) return 0; } +#elif defined(PLATFORM_FLAVOR_mx6slevk) +static int board_imx_tzasc_configure(vaddr_t addr) +{ + tzc_init(addr); + + tzc_configure_region(0, 0x00000000, + TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | + TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); + tzc_configure_region(1, 0x80000000, + TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_2G) | + TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_NS_RW); + tzc_configure_region(2, 0x9e000000, + TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | + TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW); + tzc_configure_region(3, 0x9fe00000, + TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_2M) | + TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); + + tzc_dump_state(); + + return 0; +} #elif defined(PLATFORM_FLAVOR_mx7dsabresd) static int board_imx_tzasc_configure(vaddr_t addr) { |