diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-11 15:36:07 +0000 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-11 16:19:45 +0000 |
| commit | 74c7ca466d8133cbac5a6ec5d0f3a64413077281 (patch) | |
| tree | 4506c97647db7ef40e9a8ecccf2679e20676c9cd | |
| parent | d079f702fb167d2dbedef4e2ac7ab571268b2949 (diff) | |
bl2-el3: Fix exit to bl32 via eretlinaro-imx7-01
On two different sorts of i.MX7 boards the WaRP7 and PicoPi we have
observed occasional failure to hand over from BL2 to BL32 i.e. from ATF to
OPTEE.
Drilling down into the failure on the subset of boards we see the failure
subsequent to eret.
The root cause of this is that eret only populates the CPSR with the SPSR
when executing in Hyp Mode and not in Secure mode.
Populating CPSR from SPSR when NS = 0 with eret is not architecturally
defined.
This patch addresses the problem by specifically loading CPSR with the
required target mode, prior to executing eret.
Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
| -rw-r--r-- | bl2/aarch32/bl2_el3_entrypoint.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/bl2/aarch32/bl2_el3_entrypoint.S b/bl2/aarch32/bl2_el3_entrypoint.S index cc846ddf..860f0ae7 100644 --- a/bl2/aarch32/bl2_el3_entrypoint.S +++ b/bl2/aarch32/bl2_el3_entrypoint.S @@ -71,11 +71,10 @@ func bl2_run_next_image /* * Extract PC and SPSR based on struct `entry_point_info_t` - * and load it in LR and SPSR registers respectively. + * and load it in to the LR. */ ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] - ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] - msr spsr, r1 + ldr r4, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ cps #MODE32_svc @@ -84,5 +83,7 @@ func bl2_run_next_image add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET ldm r8, {r0, r1, r2, r3} + /* Load CPSR with target mode prior to eret */ + msr cpsr, r4 eret endfunc bl2_run_next_image |