diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-12 12:09:51 +0000 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-03-12 12:23:05 +0000 |
| commit | 4a4eac3def7526b9b4dac906f80f40650ce03c76 (patch) | |
| tree | 630de5f70ffb73906c1f5c88661139cf239c8e93 | |
| parent | 49109a34f2f90bae51e07827ac0686e2fc51aa9d (diff) | |
bl1-smc-handler: Ensure the full 32 bits of SPSR are programmedintegration+bl2-el3-eret-fix-v2-00
A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the full 32 bits of the SPSR to populate into the CPSR on eret.
The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.
msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the full 32 bits are programmed we need msr spsr_fsxc, r1.
Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1')
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
| -rw-r--r-- | bl1/aarch32/bl1_exceptions.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S index 6728278f..d0761417 100644 --- a/bl1/aarch32/bl1_exceptions.S +++ b/bl1/aarch32/bl1_exceptions.S @@ -71,7 +71,7 @@ debug_loop: */ ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] - msr spsr, r1 + msr spsr_fsxc, r1 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ cps #MODE32_svc |